UPD765B Datasheet PDF - NEC Electronics

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UPD765B
NEC Electronics

Part Number UPD765B
Description Single / Double Density Floppy-Disk Controller
Page 17 Pages


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NEC
NEC Electronics Inc.
uPD765A/uPD765B
Single/Double Density
Floppy-Disk Controller
Description
The uPD765A/B is an LSI floppy disk controller (FDC)
chip which contains the circuitry and control functions
for interfacing a processor to 4 floppy disk drives. It is
capableof either IBM 3740singledensity format (FM), or
IBM System 34 double density format (MFM) including
double-sided recording. The uPD765A/B provides con-
trol signals which simplify the design of an external
phase-locked loop and write precompensation circuitry.
The FDC simplifies and handles most of the burdens as-
sociated with implementing a floppy disk interface.
Hand-shaking signals are provided in the uPD765A/B
which make DMA operation easy to incorporate with the
aid of an external DMA controller chip, such as the
uPD8257. The FDC will operate in eitherthe DMA or non-
DMA mode. In the non-DMA mode the FDC generates
interrupts to !he processor every time a data byte is to
be transferred. In the DMA mode, the processor need
only load the command into the FDC and all data
transfers occur under control of the FDC and DMA
controllers.
There are 16 commands which the uPD765A/uPD765B
will execute. Most of these commands require multiple
8-bit bytes to fully specify the operation which the
processor wishes the FDC to perform. The following
commands are available.
Read Data
Read ID
Specify
Read Diagnostic
Scan Equal
Scan High or Equal
Scan Low or Equal
Version
Read Deleted Data
Write Data
Write ID (Format Write)
Write Deleted Data
Seek
Recalibrate
Sense Interrupt Status
Sense Drive Status.
Ordering Information
Device Number
uPD765AC2
uPD765B
Package Type
40-pin plastic DIP
40-pin plastic DIP
Max Freq. of Operation
8 MHz
8 MHz
Features
Address mark detection circuitry is internal to the FDC
which simplifies the phase-locked loop and read elec-
tronics. The track stepping rate, head load time, and
head unload time are user-programmable. The
uPD765A/uPD765B
offers additional features such as
multi-track and multi-side read and write commands
and single and double density capabilities.
FM, MFM Control
Variable recording length: 128,256, .8192 bytes/
sector
IBM-compatible format (single- and double-
sided, single- and double-density)
Multi-sector and multi-track transfer capability
Drive up to 4 floppy or micro floppydisk drives
Data scan capability-will scan a single sector or
an entire cylinder comparing byte-for-byte host
memory and disk data
Data transfers in DMA or non-DMA mode
Parallel seek operations on up to four drives
Compatible with uPD8080/85, uPD8086/88,
and uPD780 (Z80@) microprocessors
V-series
Single-phase clock: 8 MHz maximum
3 +5V only
Z80 is a registered trademark of the Zilog Corporation
Pin Configuration
NECEL-000324
5-3



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uPD765A/uPD765B
NEC
Pin Identification
No.
1
2
3
4
5
6-13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28 29
30
31, 32
33
34
Symbol
RESET
RD
WR
CS
A0
DB0-DB7
DRQ
DACK
TC
INDEX
INT
CLK
GND
WCLK
WINDOW
R DATA
SYNC
WE
MFM
SIDE
USn US1
WDATA
P S 0 PS1
FLT/TRK0
WPRT/2SIDE
35 READY
36 HDLD
3 7 FLTR/STEP
38 LCT/DIR
39 m / S E E K
40 k c
Function
Reset input
Read control input
Write control input
Chip select input
Data or status select input
Bidirectional data bus
DMA request output
DMA acknowledge input
Terminal count input
Index input
Interrupt request output
Clock input
Ground
Write clock input
Read data window input
Read data input
VCO sync output
Write enable output
MFM output
Head select output
FDD unit select output
Write data output
Preshift output
Fault/track zero input
Write protect/two side
input
R e a d y input
Head load output
Fault reset/step output
Low current direction
output
Read/write/ seek output
DC power ( +5 V)
Pin Functions
RESET (Reset)
The RESET input places the FDC in the idle state. It re-
sets the output lines to the FDD to 0 (low), except PSO, 1
and WDATA (undefined), INT and DRQ also go low;
DBO-7 goes to an input state. It does not affect SRT,
HUT, or HLT in the Specify command. If the RDY input is
held high during reset, the FDC will generate an inter-
rupt within 1.024ms. To clear this interrupt, use the
Sense Interrupt Status command.
RD (Read Strobe)
The RD input allows the transfer of data from the FDC
to the data bus when low and either CSor DACK is
asserted.
WR (Write Strobe)
TheWR input allows the transfer of data to the FDC
from the data bus when low. Disabled when CSis high.
A0 (Data/Status Select)
The A0 input selects the data register (A0 = 1) or status
register (A0=O) contents to be accessed through the
data bus.
CS(Chip Select)
The FDC is selected when CSis low, enabling RD and
WR.
DBo-DB7 (Data Bus)
DBo-DB7 are a bidirectional 8-bit data bus. Disabled
when CSis high.
DRQ (DMA Request)
The FDC asserts the DRQ output high to request a DMA
transfer.
DACK (DMA Acknowledge)
When the DACK input is low, a DMA cycle is active and
the controller is performing a DMA transfer.
TC (Terminal Count)
When theTC input is high, it indicates the termination of
a DMA transfer. It terminates data transfer during Read/
Write/Scan commands in DMA or interrupt mode.
INDEX (Index)
The INDEX input goes high at the beginning of a disk
track.
INT (Interrupt)
The INT output is FDC’s interrupt request. In Non-DMA
mode, the signal is output for each byte. In DMA mode,
it is output at the termination of a command operation.
CLK (Clock)
CLK is the input for the FDC’s single-phase, lTL-level
squarewave clock: 8 MHz or 4 MHz. (Requires a pull-up
resistor.)



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NEC
uPD765A/uPD765B
WCLK (Write Clock)
The WCLK input sets the data write rate to the FDD. It is
500 kHz for FM, 1 MHz for MFM drives, for 8 MHz opera-
tion of the FDC; 250kHz FM or 500 kHz MFM for 4 MHz
FDC operation.
This signal must be input for read and write cycles
WCLK’s rising edge must be synchronized with CLK’s
rising edge, except for the uPD765B.
WINDOW (Read Data Window)
The WINDOW input is generated by the phase-locked
loop (PLL). It is used to sample data from the FDD and in
distinguishing between clock and data bits in the FDC.
RDATA (Read Data)
The RDATA input is the read data from the FDD,
containing clock and data bits. To avoid a deadlock
situation, input RDATA and WINDOW together.
WDATA (Write Data)
WDATA is the serial clock and data output to the FDD.
WE (Write Enable)
The WE output enables write data into the FDD.
SYNC (VCO Sync)
The SYNC output inhibits the VCO in the PLL when low,
enables it when high.
MFM (MFM Mode)
The MFM output shows the VCO’s operation mode. It is
high for MFM, low for FM.
SIDE (Head Select)
Head 1 is selected when the SIDE output is 1 (high), head
0 is selected when SIDE is 0 (low).
U S 0 US1 (Unit Select 0,1)
The US0 and US1 outputs select up to 4 floppy disk drive
units using an external decoder.
PS0, PS1 (Preshift 0,1)
The PS0 and PS1 outputs are the write precompensation
request signals for MFM mode. They determine early,
late, and normal times for WDATA shifting.
READY (Ready)
The READY input indicates that the FDD is ready to re-
ceive data.
HDLD (Head Load)
The HDLD output is the command which causes the
read/write head in the FDD to contact the diskette.
FLT/TRKO (Fault/Track 0)
In the read/write mode, the FLT input detects FDD fault
conditions. In the seek mode, TRKO indicates track 0
head position.
WPRT/2SlDE (Write Protect/Two Side)
In the read/write mode, the WPRT input senses write
protected status (at the drive or media.) In the seek
mode, 2SIDE senses two-sided media.
FLTR/STEP (Fault Reset/Step)
In the read/write mode, the FLTR output resets the fault
flip-flop in the FDD. In the seek mode, STEP outputs
step pulses to move the head to another cylinder. A fault
reset pulse is issued at the beginning or each Read or
Write command prior to the HDLD signal.
LCT/DlR (Low Current/Direction)
In the read/write mode, the LCT output indicates that
the R/W head is positioned at cylinder 42 or greater. In
the seek mode, the DIR output determines the direction
the head will move in when it receives a step pulse. If
DIR is 0, seeks are performed in the outward direction;
DIR is 1, seeks are performed in the inward direction.
RWlSEEK (Read/Write/Seek)
The RW/SEEK output specifies the read/write mode
when low, and the seek mode when high.
GND (Ground)
Ground.
Vcc(+5v)
+5 V power supply.
5-5



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uPD765AIuPD765B
NEC
Block Diagram
Absolute Maximum Ratings
TA = 250C
Power supply voltage, VCC
- 0 5to +7v
Input voltage, V1
-0.5 to +7v
Output voltage, VO
Operating temperature, TOpT
- 0 . 5 1 0 +7v
- 1OOC to +7ooc
Storage temperature, TSTG
-65°C to +150°C
Comment: Exposing the device to stresses above those listed
in the Absolute Maximum Ratings could cause permanent
damage. The device should not be operated under conditions
outside the limits described in the operational sections of this
specification. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
DC Characteristics
Th= -1O’C to +70°C,Vc_c_= +5V%lO%
Parameter
Limits
Symbol Min Typ Max Unit
Input voltage
-0.5
v
IOW
Input voltage
high
VIH
2.0
5v
Output voltage
low
0.45 V
Voltage
2.4
kc V
Input voltage
low (CLK +
WCLK)
Input voltage
high
(CLK + WCLK)
Supply current
kc)
0.5 0.65 V
v
150
140
Input load
current high
Input load
current low
Output leakage
current high
Output leakage
current low
10
-10
10
-10
Teal
Conditions
Capacitance
Parameter
Input clock
Symbol
Limits
Min Typ Max Unit
20 pF
Input
capacitance
output
capacitance
COUT
Note:
(1) All pinsexcept pin under test tied to
10 pF
20 pF
AC ground.
Test
Conditions
(Note 1)
(Note 1)
[Note 1)
5-6



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