UPD4564163 Datasheet PDF - NEC

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UPD4564163
NEC

Part Number UPD4564163
Description 64M-bit Synchronous DRAM
Page 30 Pages


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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4564441, 4564841, 4564163
64M-bit Synchronous DRAM
4-bank, LVTTL
Description
The µPD4564441, 4564841, 4564163 are high-speed 67,108,864-bit synchronous dynamic random-access
memories, organized as 4,194,304 × 4 × 4, 2,097,152 × 8 × 4, 1,048,576 ×16 × 4 (word × bit × bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
Features
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by A12 and A13 (Bank Select)
Byte control (×16) by LDQM and UDQM
Programmable Wrap sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable /CAS latency (2 and 3)
Automatic precharge and controlled precharge
CBR (auto) refresh and self refresh
• ×4, ×8, ×16 organization
Single 3.3 V ± 0.3 V power supply
LVTTL compatible inputs and outputs
4,096 refresh cycles / 64 ms
Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M12621EJCV0DS00 (12th edition)
Date Published January 2000 NS CP (K)
Printed in Japan
The mark shows major revised points.
©
1997



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5 Ordering Information
Part number
µPD4564441G5-A80-9JF
µPD4564441G5-A10-9JF
µPD4564441G5-A10B-9JF
µPD4564841G5-A80-9JF
µPD4564841G5-A10-9JF
µPD4564841G5-A10B-9JF
µPD4564163G5-A80-9JF
µPD4564163G5-A10-9JF
µPD4564163G5-A10B-9JF
µPD4564441, 4564841, 4564163
Organization
(word × bit × bank)
4M × 4 × 4
2M × 8 × 4
1M × 16 × 4
Clock frequency
MHz (MAX.)
125
100
100
125
100
100
125
100
100
Package
54-pin Plastic TSOP (II)
(10.16mm (400))
2 Data Sheet M12621EJCV0DS00



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µPD4564441, 4564841, 4564163
5 Part Number
[ x4, x8 ]
µPD4564841G5 - A80
NEC Memory
Synchronous DRAM
Memory density
64 : 64M bits
Organization
4 : x4
8 : x8
Minimum cycle time
80 : 8 ns (125 MHz)
10 : 10 ns (100 MHz)
10B : 10 ns (100 MHz)
Number of banks
4 : 4 banks
Interface
1 : LVTTL
[ x16 ]
163
Low voltage
A : 3.3 ± 0.3 V
Package
G5 : TSOP (II)
Organization
16 : x16
Number of banks
and Interface
3 : 4 banks, LVTTL
Data Sheet M12621EJCV0DS00
3



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µPD4564441, 4564841, 4564163
Pin Configurations
/xxx indicates active low signal.
[µPD4564441]
54-pin Plastic TSOP (II) (10.16mm (400))
4M words × 4 bits × 4 banks
VCC
NC
VCCQ
NC
DQ0
VSSQ
NC
NC
VCCQ
NC
DQ1
VSSQ
NC
VCC
NC
/WE
/CAS
/RAS
/CS
A13
A12
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 Vss
53 NC
52 VssQ
51 NC
50 DQ3
49 VccQ
48 NC
47 NC
46 VssQ
45 NC
44 DQ2
43 VccQ
42 NC
41 Vss
40 NC
39 DQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 Vss
A0 to A13 Note : Address inputs
DQ0 to DQ3 : Data inputs / outputs
CLK : Clock input
CKE
: Clock enable
/CS : Chip select
/RAS
: Row address strobe
/CAS
: Column address strobe
/WE : Write enable
DQM
: DQ mask enable
VCC : Supply voltage
VSS : Ground
VCCQ
: Supply voltage for DQ
VSSQ
: Ground for DQ
NC : No connection
Note A0 to A11 : Row address inputs
A0 to A9 : Column address inputs
A12, A13 : Bank select
4 Data Sheet M12621EJCV0DS00



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