ELECTRICAL CHARACTERISTICS (cont): Unless otherwise specified,TA = 0°C to 70°C for UCC3808-X, –40°C to 85°C
for UCC2808-X and –55°C to 125°C UCC1808-X, VDD = 10V (Note 6), 1µF capacitor from VDD to GND, Oscillator R = 22kΩ, C =
330pF. TA = TJ.
Soft Start Section
COMP Rise Time
FB = 1.8V, Rise from 0.5V to 4V
VDD < Start Threshold
Operating Supply Current
FB = 0V, CS = 0V (Note 5 and 6)
VDD Zener Shunt Voltage
IDD = 10mA
Note 1: Measured at RC. Signal amplitude tracks VDD.
Note 2: Gain is defined by
Note 3: Parameter measured at trip point of latch with FB at 0V.
Note 4: Start threshold and Zener Shunt threshold track one another.
Note 5: Does not include current in the external oscillator network.
Note 6: For UCCx808-1, set VDD above the start threshold before setting at 10V.
MIN TYP MAX UNITS
130 260 µA
1 2 mA
13 14 15
COMP: COMP is the output of the error amplifier and the
input of the PWM comparator. The error amplifier in the
UCC3808 is a true low-output impedance, 2MHz opera-
tional amplifier. As such, the COMP pin can both source
and sink current. However, the error amplifier is internally
current limited, so that zero duty cycle can be externally
forced by pulling COMP to GND.
The UCC3808 family features built-in full cycle soft start.
Soft start is implemented as a clamp on the maximum
CS: The input to the PWM and overcurrent comparators.
The overcurrent comparator is only intended for fault
sensing. Exceeding the overcurrent threshold will cause a
soft start cycle.
FB: The inverting input to the error amplifier. For best sta-
bility, keep FB lead length as short as possible and FB
stray capacitance as small as possible.
GND: Reference ground and power ground for all func-
tions. Due to high currents, and high frequency operation
of the UCC3808, a low impedance circuit board ground
plane is highly recommended.
OUTA and OUTB: Alternating high current output stages.
Both stages are capable of driving the gate of a power
MOSFET. Each stage is capable of 500mA peak source
current, and 1A peak sink current.
The output stages switch at half the oscillator frequency,
in a push/pull configuration. When the voltage on the RC
pin is rising, one of the two outputs is high, but during fall
time, both outputs are off. This "dead time" between the
two outputs, along with a slower output rise time than fall
time, insures that the two outputs can not be on at the
same time. This dead time is typically 60ns to 200ns and
is depended upon the values of the timing capacitor and
The high-current output drivers consist of MOSFET out-
put devices, which can switch from VDD to GND. Each
output stage also provides a very low impedance to over-
shoot and undershoot. This means that in many cases,
external schottky clamp diodes are not required.
RC: The oscillator programming pin. The UCC3808’s os-
cillator tracks VDD and GND internally, so that variations
in power supply rails minimally affect frequency stability.
Figure 1 shows the oscillator block diagram.
Only two components are required to program the oscilla-
tor, a resistor (tied to the VDD and RC), and a capacitor
(tied to the RC and GND). The approximate oscillator fre-
quency is determined by the simple formula
The oscillator generates a sawtooth waveform on RC. During
the RC rise time, the output stages alternate on time, but both
stages are off during the RC fall time.
The output stages switch at 1/2 the oscillator frequency, with
guaranteed duty cycle of < 50% for both ouputs.
Figure 1. Block Diagram for Oscillator