TMP91PW11 Datasheet PDF - Toshiba


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TMP91PW11
Toshiba

Part Number TMP91PW11
Description CMOS 16-Bit Microcontroller
Page 28 Pages

TMP91PW11 datasheet pdf
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TMP91PW11
Low Voltage/Low Power CMOS 16-bit Microcontroller
TMP91PW11F
1. Outline and Device Characteristics
The TMP91PW11 is OTP type MCU which includes 128 Kbyte One-time PROM. Using the
adapter-socket, you can write and verify the data for the TMP91CW11 by general EPROM
programmer.
The TMP91PW11 has the same pin-assignment as the TMP91CW11 (Mask ROM type).
Writing the program to Built-in PROM, the TMP91PW11 operates as the same way as the
TMP91CW11.
MCU
TMP91PW11F
ROM
OTP 128 Kbyte
RAM
4 Kbyte
Package
P-LQFP100-1414-0.50C
Adapter Socket
BM11129
000707EBP1
For ADiscussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality
and Reliability Assurance / Handling Precautions.
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in
general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of
the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system,
and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or
damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the
most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling
Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy
control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be mADe at the customer’s own risk.
The products described in this document are subject to the foreign exchange and foreign trADe laws.
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION
or others.
The information contained herein is subject to change without notice.
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by
Philips.
91PW11-1
2001-08-06



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TMP91PW11
ADTRG
AN0 to AN7
(P50 to P57)
AVCC
AVSS
VREFL
VREFH
SO0 (P93)
SI0 (P94)
SCK0 (P95)
SO1 (P42)
SI1 (P41)
SCK1 (P40)
TXD2 (P60)
RXD2 (P61)
SCK2 (P62)
TXD3 (P63)
RXD3 (P64)
SCK3 (P65)
TXD4 (P66)
RXD4 (P67)
SDA/SO5 (P90)
SCL/SI5 (91)
SCK5 (P92)
TI0 (P70)
TO1 (P71)
TO2(P72)
TO3 (P73))
INT4/TI4 (P80)
INT5/TI5 (P81)
TO4 (P82)
TO5 (P83)
INT6/TI6 (P84)
INT7/TI7 (P85)
TO6 (P86)
10-Bit 8ch
AD
Converter
Serial I/ O
(CH.0)
Serial I/ O
(CH.1)
Serial I/O
(CH. 2)
CPU (TLCS-900L1)
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
WA
BC
DE
HL
IX
IY
IZ
SP
32 bits
SR F
PC
Serial I/O
(CH. 3)
SERIAL I/O
(CH. 4)
Serial Bus
Interface
Controller
8-Bit Timer
(Timer 0)
8-Bit Timer
(Timer 1)
4-KB RAM
OSC1
Clock
Gear
OSC2
Port 3
Port 0
Port 1
Port 2
Port A
8-Bit Timer
(Timer 2)
8-Bit Timer
(Timer 3)
128-KB PROM
Watchdog
Timer
16-Bit Timer
(Timer 4)
16-Bit Timer
(Timer 5)
Real Time
Counter
Interrupt
Controller
CS/WAIT
Controller
(3-Block)
Figure 1.1 TMP91PW11 block diagram
VCC [3]
VSS [3]
X1
X2
XT1 (P96)
XT2 (P97)
CLK
ALE
EA
AM8/16
RESET
RD (P30)
WR (P31)
HWR (P32)
WAIT (P33)
BUSRQ (P34)
BUSAK (P35)
R/W (P36)
P37
AD0 to AD7
(P00 to P07)
AD8/A8 to AD15/A15
(P10 to P17)
A0/A16 to A7/A23
(P20 to P27)
PA0 to PA6
SCOUT (PA7)
WDTOUT
NMI
INT0 (P87)
CS0 (P40)
CS1 (P41)
CS2 (P42)
91PW11-2
2001-08-06



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TMP91PW11
2. Pin Assignment and Pin Functions
The assignment of input/output pins for the TMP91PW11F, their names and outline functions
are described below.
2.1 Pin Assignment
Figure 2.1.1 shows pin assignment of TMP91PW11F.
Programmable
Pull Pull TMP91PW11
Up Down
P66/TXD4
Pin
No.
89
P67/RXD4
VSS
P50/AN0
90
91
92
P51/AN1
P52/AN2
93
94
P53/AN3/ADTRG 95
ADC
P54/AN4
P55/AN5
P56/AN6
P57/AN7
VREFH
96
97
98
99
100
Timer
SIO
VREFL
AVSS
AVCC
NMI
P70/TI0
P71/TO1
P72/TO2
P73/TO3
P80/INT4/TI4
P81/INT5/TI5
P82/TO4
P83/TO5
P84/INT6/TI6
P85/INT7/TI7
P86/TO6
P87/INT0
P90/SDA/SO5
P91/SCL/SI5
P92/SCK5
P93/SO0
P94/SI0
P95/SCK0
AM8/16
CLK
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Clock
mode
VSS
X1
X2
EA
RESET
P96/XT1
P97/XT2
TEST1
TEST2
PA0
PA1
PA2
26
27
28
29
30
31
32
33
34
35
36
37
top view
LQFP100
Figure 2.1.1 Pin assignment
Pin
No.
TMP91PW11
88 P65/CTS3/SLCK3
87 P64/RXD3
86 P63/TXD3
85 P62/CTS2/SLCK2
84 P61/RXD2
83 P60/TXD2
82 P42/CS2/SO1
81 P41/CS1/SI1
80 P40/CS0/SCK1
79 P37
78 P36/R/W
77 P35/BUSAK
76 P34/BUSRQ
Programmable
Pull Pull
Down Up
SIO
75 P33/WAIT
74 P32/HWR
73 P31/WR
72 P30/RD
71 P27/A7/A23
70 P26/A6/A22
69 P25/A5/A21
68 P24/A4/A20
67 P23/A3/A19
66 P22/A2/A18
65 P21/A1/A17
64 P20/A0/A16
63 VCC
62 VSS
61 WDTOUT
60 P17/AD15/A15
59 P16/AD14/A14
58 P15/AD13/A13
57 P14/AD12/A12
56 P13/AD11/A11
55 P12/AD10/A10
54 P11/AD9/A9
53 P10/AD8/A8
52 P07/AD7
51 P06/AD6
50 P05/AD5
49 P04/AD4
48 P03/AD3
47 P02/AD2
46 P01/AD1
45 P00/AD0
44 VCC
43 ALE
42 PA7/SCOUT
41 PA6
40 PA5
39 PA4
38 PA3
91PW11-3
2001-08-06



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2.2 Pin Names and Functions
The names of input/output pins and their functions are described below.
TMP91PW11
Pin name
P00 to P07
AD0 to AD7
P10 to P17
AD8 to AD15
A8 to A15
P20 to P27
Number
of pins
8
8
8
A0 to A7
A16 to A23
P30
RD
P31
WR
P32
HWR
P33
WAIT
P34
BUSRQ
1
1
1
1
1
P35
BUSAK
1
P36
R/ W
P37
P40
CS0
SCK1
1
1
1
Table 2.2.1 Pin names and functions (1/4)
I/O Function
I/O Port 0: I/O port that allows selection of I/O on a bit basis
Tri-state Address/data (lower): Bits 0 to 7 of address/data bus
I/O Port 1: I/O port that allows selection of I/O on a bit basis
Tri-state Address data (upper): Bits 8 to 15 of address/data bus
Output Address: 8 to 15 of address bus
I/O Port 2: I/O port that allows selection of I/O on a bit basis
(with pull-up resistor)
Output Address: Bits 0 to 7 of address bus
Output Address: Bits 16 to 23 of address bus
Output Port 30: Output port
Output Read: Strobe signal for reading external memory
Output Port 31: Output port
Output Write: Strobe signal for writing data on pins AD0 to 7
I/O Port 32: I/O port (with pull-up resistor)
Output High write: Strobe signal for writing data on pins AD8 to 15
I/O Port 33: I/O port (with pull-up resistor)
Input Wait: Pin used to request CPU bus wait
I/O Port34: I/O port(with pull-up resistor)
Input Bus request: Signal used to request high impedance for AD0 to 15, A0-23,
RD , WR , HWR , R/ W , RAS , CS0 , CS1, and CS2 pins.
(For external DMAC)
I/O Port 35: I/O port (with pull-up resistor)
Output Bus acknowledge: Signal indicating that AD0 to 15, A0 to 23, R RD , WR ,
HWR , R/ W , RAS , CS0 , CS1, and CS2 pins are at high impedance after
receiving BUSRQ. (For external DMAC)
I/O Port 36: I/O port (with pull-up resistor)
Output Read/write: 1 represents read or dummy cycle; 0, write cycle.
I/O Port 37: I/O port (with pull-up resistor)
I/O Port 40: I/O port (with pull-up resistor)
Output Chip select 0: Outputs 0 when address is within specified address area.
I/O Serial clock I/O 1
Note: This device’s built-in memory or built-in I/O cannot be accessed with the external DMA controller,
using the BUSRQ and BUSAK signals.
91PW11-4
2001-08-06




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