TMP91CU10 Datasheet PDF - Toshiba


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TMP91CU10
Toshiba

Part Number TMP91CU10
Description CMOS 16-Bit Microcontroller
Page 19 Pages

TMP91CU10 datasheet pdf
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Low-Voltage CMOS 16-Bit Microcontrollers
TMP91CU10F
TMP91CU10
1. Outline and Device Characteristics
The TMP91CU10 is an original Toshiba TLCS-900/L1 Series 16-bit microcontroller. The
TMP91CU10 integrates a 16-bit CPU, ROM, RAM, multi-functional timer and event counter,
general-purpose serial interface, an A/D converter and various other units in a single chip, and
has been developed for controlling medium- to large-scale equipment.
The TMP91CU10 is housed in a 100-pin mini flat package.
The device characteristics are as follows:
(1) Original high-speed 16-bit CPU (900/H CPU)
TLCS-90/900 instruction mnemonics (upwards compatible)
16-Mbyte linear address space
General-purpose registers and register bank system
16-bit multiplication/division and bit transfer/arithmetic instructions
High-speed µDMA: 4 channels (1.18 µs at 13.5 MHz) (1.0 µs at 16 MHz)
(2) Minimum instruction execution time
400 ns at 10 MHz (VCC = 2.0 V) for mask ROM products only
296 ns at 13.5 MHz (VCC = 3.0 V)
(3) Internal RAM: 3 Kbytes
Internal ROM: 96 Kbytes
(4) External memory expansion
Can be expanded up to 16 Mbytes (for both programs and data).
AM8/16 pin (selects the external data bus width)
Can mix 8- and 16-bit external data buses (dynamic bus sizing) .
(5) Chip Select and Wait controller: 3 blocks
(6) 8-bit timer: 8 channels
Including event count function: 2 channels
(7) 16-bit timer and event counter: 2 channels
(8) General-purpose serial interface: 3 channels
UART and Synchronous modes
(9) (10-bit A/D converter: 8 channels
980910EBP1
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled
Quality and Reliability Assurance / Handling Precautions.
TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in
general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility
of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or
failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs,
please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products
specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability
Handbook.
The products described in this document are subject to the foreign exchange and foreign trade laws.
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed
by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result
from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA
CORPORATION or others.
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(10) Watchdog timer
(11) Interrupt functions
2 CPU interrupts (SWI instruction and Illegal instruction)
26 internal interrupts
7-level priority can be set.
10 external interrupts
7-level priority can be set.
(12) I/O ports: 80 pins
(13) Standby function: 4 Halt modes (Run, Idle2, Idle1, Stop)
(14) Clock gear function
Clock gear: High-frequency clock can be changed from fc to fc/16.
Dual clock operation
(15) Low operating voltage
2.0 to 3.6 V
(16) Package
Compact 14 mm × 14 mm × 1.4 mm (0.5 mm pitch)
TMP91CU10
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TMP91CU10
AN0 to AN7
(P50 to P57)
AVcc
AVss
VREFL
VREFH
TXD0 (P90)
RXD0 (P91)
SCLK0/ CTS0 (P92)
TXD1 (P93)
RXD1 (P94)
SCLK1 (P95)
TXD2 (P60)
RXD2 (P61)
SCLK2/ CTS2 (P62)
TI0/INT1
(P70)
TO1 (P71)
TO3/INT2
(P72)
TI4/INT3
(P73)
TO5 (P74)
TO7/INT4
(P75)
10-BIT 8-CH
A/D
CONVERTER
SERIAL I/O
(CH.0)
SERIAL I/O
(CH.1)
SERIAL I/O
(CH.2)
8-BIT TIMER
(TIMER 0)
8-BIT TIMER
(TIMER 1)
CPU (TLCS-900/H)
XWA
XBC
XDE
XHL
XIX
XIY
XSP
WA
BC
DE
HL
IX
IY
IZ
SP
32 bits
SR F
PC
WATCHDOG
TIMER
3 KB RAM
OSC1
Clock
Gear
OSC2
PORT 0
PORT 1
PORT 2
DVCC [3]
DVSS [3]
X1
X2
XT1 (P96)
XT2 (P97)
CLK
ALE
EA
RESET
RD (P30)
WR (P31)
HWR (P32)
BUSRQ (P34)
BUSAK (P35)
R/ W (P36)
AM8/ 16
P37
(P00 to P07)
AD0 to AD7
(P10 to P17)
AD8/A8 to AD15/A15
(P20 to P27)
A0/A16 to A7/A23
8-BIT TIMER
(TIMER 2)
8-BIT TIMER
(TIMER 3)
8-BIT TIMER
(TIMER 4)
8-BIT TIMER
(TIMER 5)
8-BIT TIMER
(TIMER 6)
8-BIT TIMER
(TIMER 7)
96 KB RAM
PORT A
PORT 6
CS/WAIT
CONTROLLER
(3-BLOCK)
INTERRUPT
CONTROLLER
16-BIT TIMER
(TIMER 8)
PA0 to PA7
P63, P65 to P67
CS0 (P40)
CS1 (P41)
CS2 (P42)
WAIT (P33)
NMI
INTO (P64)
TI8/INT5 (P80)
TI9/INT6 (P81)
TO8 (P82)
TO9 (P83)
16-BIT TIMER
(TIMER 9)
TIA/INT7 (P84)
TIB/INT8 (P85)
TOA/TOB (P86)
( ): Default function after reset
Figure 1.1 TMP91CU10F Block Diagram
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TMP91CU10
2. Pin Assignment and Functions
The assignment of input and output pins for the TMP91CU10, their names and functions are
described as follows:
2.1 Pin Assignment
Figure 2.1.1 shows the pin assignment of the TMP91CU10.
P66
P67
DVSS
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
VREFH
89
90
91
92
93
94
95
96
97
98
99
100
VREFL
AVSS
AVCC
P70/TI0/INT1
P71/TO1
P72/TO3/INT2
P73/TI4/INT3
P74/TO5
P75/TO7/INT4
P80/TI8/INT5
P81/TI9/INT6
P82/TO8
P83/TO9
P84/TIA/INT7
P85/TIB/INT8
P86/TOA/TOB
P90/TXD0
P91/RXD0
P92/SCLK0/CTS0
P93/TXD1
P94/RXD1
P95/SCLK1
AM8/16
CLK
DVCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DVSS
X1
X2
EA
RESET
P96/XT1
P97/XT2
TEST1
TEST2
PA0
PA1
PA2
26
27
28
29
30
31
32
33
34
35
36
37
88 P65
87 P64/INT0
86 P63
85 P62/SCLK2/CTS2
84 P61/RXD2
83 P60/TXD2
82 P42/CS2
81 P41/CS1
80 P40/CS0
79 P37
78 P36/R/W
77 P35/BUSAK
76 P34/BUSRQ
75 P33/WAIT
74 P32/HWR
73 P31/WR
72 P30/RD
71 P27/A7/A23
70 P26/A6/A22
69 P25/A5/A21
68 P24/A4/A20
67 P23/A3/A19
66 P22/A2/A18
65 P21/A1/A17
64 P20/A0/A16
63 DVCC
62 DVSS
61 NMI
60 P17/AD15/A15
59 P16/AD14/A14
58 P15/AD13/A13
57 P14/AD12/A12
56 P13/AD11/A11
55 P12/AD10/A10
54 P11/AD9/A9
53 P10/AD8/A8
52 P07/AD7
51 P06/AD6
50 P05/AD5
49 P04/AD4
48 P03/AD3
47 P02/AD2
46 P01/AD1
45 P00/AD0
44 DVCC
43 ALE
42 PA7
41 PA6
40 PA5
39 PA4
38 PA3
Figure 2.1.1 Pin Assignment diagram
91CU10-4




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