TEA1795T Datasheet PDF - NXP


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TEA1795T
NXP

Part Number TEA1795T
Description GreenChip synchronous rectifier controller
Page 14 Pages

TEA1795T datasheet pdf
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TEA1795T
GreenChip synchronous rectifier controller
Rev. 1 — 4 November 2010
Product data sheet
1. General description
The TEA1795T is a member of the new generation of Synchronous Rectifier (SR)
controller ICs for switched mode power supplies. Its high level of integration enables the
design of a cost-effective power supply with a minimum number of external components.
The TEA1795T is a dedicated controller IC for synchronous rectification on the secondary
side of resonant converters. It has two driver stages for driving the SR MOSFETs, which
are rectifying the outputs of the central tap secondary transformer windings.
The two gate driver stages have their own sensing inputs and operate independently of
each other.
The TEA1795T is fabricated in a Silicon On Insulator (SOI) process.
2. Features and benefits
2.1 Distinctive features
„ Accurate synchronous rectification functionality
„ Wide supply voltage range (8.5 V to 38 V)
„ Separate sense inputs for sensing the drain and source voltage of each SR MOSFET
„ High level of integration, resulting in a minimum external component count
„ High driver output voltage of 10 V to drive all MOSFET brands to the lowest RDSon
2.2 Green features
„ Low current consumption
„ High system efficiency from no load to full load
2.3 Protection features
„ UnderVoltage Protection (UVP)
3. Applications
The TEA1795T is intended for resonant power supplies. In such applications, it can drive
two external synchronous rectifier MOSFETs which replace diodes for the rectification of
the voltages on the two secondary windings of the transformer. It can be used in
applications such as:
„ Adapters
„ ATX power supplies



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NXP Semiconductors
TEA1795T
GreenChip synchronous rectifier controller
„ Server power supplies
„ LCD television
„ Plasma television
4. Ordering information
Table 1. Ordering information
Type number
Package
Name
Description
TEA1795T/N1
SO8
plastic small outline package; 8 leads; body width 3.9 mm
5. Block diagram
Version
SOT96-1
VCC
7
UVLO
SUPPLY
AND
BIAS
control A
4
DSA
TIMER
0.4 μs
RQ
& SQ
1
SSA
25 mV
12 mV
220 mV
TEA1795T
TIMER
0.5 μs
3
DRIVER
GDA
control B
DSB 5
TIMER
0.4 μs
SSB 8
25 mV
12 mV
220 mV
RQ
TIMER
0.5 μs
& SQ
6
GDB
DRIVER
Fig 1. Block diagram
2
GND
001aal796
TEA1795T
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 November 2010
© NXP B.V. 2010. All rights reserved.
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6. Pinning information
6.1 Pinning
TEA1795T
GreenChip synchronous rectifier controller
Fig 2. Pin configuration
SSA 1
GND 2
GDA 3
DSA 4
8 SSB
TEA1795T
7 VCC
6 GDB
5 DSB
014aaa976
6.2 Pin description
Table 2.
Symbol
SSA
GND
GDA
DSA
DSB
GDB
VCC
SSB
Pin description
Pin
1
2
3
4
5
6
7
8
Description
source sense input MOSFET A
ground
gate driver output MOSFET A
drain sense input for synchronous timing MOSFET A
drain sense input for synchronous timing MOSFET B
gate driver output MOSFET B
supply voltage
source sense input MOSFET B
7. Functional description
7.1 Introduction
The TEA1795T is a controller for synchronous rectification to be used in resonant
applications. It can drive two synchronous rectifier MOSFETs on the secondary side of the
central tap transformer winding. A typical configuration is shown in Figure 3.
TEA1795T
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 November 2010
© NXP B.V. 2010. All rights reserved.
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TEA1795T
GreenChip synchronous rectifier controller
Vin
Qprim1
PRIMARY
SIDE
CONTROLLER
CHB
Qprim2
TR
Vout
RDRNSENSE1
RDRNSENSE2
Qsec1
IC1 VCC
DSA
DSB
GDA TEA1795T GDB
SSA
SSB
Qsec2
Cout
GND
001aal797
Fig 3. TEA1795T: typical configuration
7.2 Start-up and UnderVoltage LockOut (UVLO)
The IC leaves the UVLO state and activates the synchronous rectifier circuitry when the
voltage on the VCC pin is above Vstartup (8.5 V typical). When the voltage drops below
8.0 V (typical), the UVLO state is reentered and the SR MOSFET gate driver outputs are
actively kept low.
7.3 Supply management
All (internal) reference voltages are derived from a temperature compensated, on-chip
band gap circuit.
7.4 Synchronous rectification (DSA, SSA, DSB and SSB pins)
The voltages present between the drain and source terminals of the SR MOSFETs are
used to derive the timing for the gate drive signal. The IC senses the voltage difference
between the drain sense (pins DSA and DSB) and the source sense (pins SSA and SSB)
connections. When this voltage difference is lower than Vact(drv) (220 mV typical), the
corresponding gate driver output voltage is driven high and the external SR MOSFET is
switched on.
When the external SR MOSFET is switched on, the input signals on the drain sense pins
and source sense pins are ignored during the minimum synchronous rectification active
time (tact(sr)(min), 520 ns typical). This minimizes false switch-off due to the sensing of high
frequency ringing signals at the start of the conduction phase.
TEA1795T
Product data sheet
Once this minimum synchronous rectification active time has ended, the IC monitors the
difference between the drain sense inputs and the source sense inputs. When the
difference is higher than Vreg(drv) (25 mV typical), the gate driver output voltage is
regulated to maintain this 25 mV difference between the drain sense pins and the source
sense pins. As a result, the SR MOSFET can be switched off quickly when the current
through the external SR MOSFET reaches zero.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 November 2010
© NXP B.V. 2010. All rights reserved.
4 of 14




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