TDA9935 Datasheet PDF - NXP Semiconductors


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TDA9935
NXP Semiconductors

Part Number TDA9935
Description Dual 14-bit up to 160 Msample/s 2 interpolating Digital-to-Analog Converter
Page 18 Pages

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TDA9935
www.DataSheet4U.com
Dual 14-bit, up to 160 Msample/s, 2 × interpolating
Digital-to-Analog Converter (DAC)
Rev. 04 — 17 September 2007
Product data sheet
1. General description
The TDA9935 is optimized to reduce architecture complexity and overall system cost.
Thanks to its direct IF conversion capabilities, it leads dynamic performance in
multi-carrier support. With an internal sampling rate up to 160 Msample/s, TDA9935 is an
extremely competitive solution for WCDMA, CDMA2000 and GSM/EDGE transmitters, as
well as high data rate radio services like WLL, LMDS and BWA.
2. Features
I Dual 14-bit resolution
I SFDR = 80 dBc at 2.5 MHz
I Input data rate up to 80 Msample/s
I 2 × interpolation filter
I Output data rate up to 160 Msample/s
I Single 3.3 V power supply
I Low noise capacitor-free integrated PLL
I Low power dissipation
I HTQFP80 package
I Ambient temperature from 40 °C to +85 °C
3. Applications
I Broadband wireless systems
I Digital radio links
I Cellular base stations
I Instrumentation



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NXP Semiconductors
TDA9935www.DataSheet4U.com
Dual 14-bit, up to 160 Msample/s, 2 × interpolating DAC
4. Ordering information
Table 1. Ordering information
Type number
Package
Name
Description
Version
TDA9935HW
HTQFP80 plastic thermal enhanced thin quad flat package; SOT841-1
80 leads; body 12 × 12 × 1 mm; exposed die pad
5. Block diagram
I13 to I0
CLK
CLKN
Q13 to Q0
TDA9935
VCCA
U/I
60
11 to 16,
19 to 24,
27, 28
14
LATCH
14
5
CLOCK
6 DRIVER
31 to 34,
37 to 42,
45 to 48
14
LATCH
14
DAC
FIR 14
73
72
(CLK × 2)
PLL
(CLK × 2)
INTERNAL 58
BAND GAP
(CLK × 2)
DAC
FIR 14
57
69
68
IVIRES
IOUT
IOUTN
GAPOUT
GAPD
QOUT
QOUTN
i.c. 2, 8
VCCD 10, 51
(1) (2) (3) (4)
VCCA
VCCA AGND DGND DEC
(1) Pins 1, 3, 61, 65, 76 and 80.
(2) Pins 4, 7, 62, 64, 66, 67, 70, 71, 74, 75, 77 and 79.
(3) Pins 9, 17, 25, 29, 30, 35, 44, 49, 50, 52, 53, 54, 55 and 56.
(4) Pins 18, 26, 36, 43, 63 and 78.
Fig 1. Block diagram
U/I
59 QVIRES
001aab119
TDA9935_4
Product data sheet
Rev. 04 — 17 September 2007
© NXP B.V. 2007. All rights reserved.
2 of 18



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6. Pinning information
6.1 Pinning
TDA9935www.DataSheet4U.com
Dual 14-bit, up to 160 Msample/s, 2 × interpolating DAC
VCCA 1
i.c. 2
VCCA 3
AGND 4
CLK 5
CLKN 6
AGND 7
i.c. 8
DGND 9
VCCD 10
I13 11
I12 12
I11 13
I10 14
I9 15
I8 16
DGND 17
DEC 18
I7 19
I6 20
TDA9935HW
DGND
60 IVIRES
59 QVIRES
58 GAPOUT
57 GAPD
56 DGND
55 DGND
54 DGND
53 DGND
52 DGND
51 VCCD
50 DGND
49 DGND
48 Q0
47 Q1
46 Q2
45 Q3
44 DGND
43 DEC
42 Q4
41 Q5
001aab120
Fig 2. Pin configuration
6.2 Pin description
Table 2.
Symbol
VCCA
i.c.
VCCA
AGND
CLK
CLKN
AGND
i.c.
DGND
Pin description
Pin Type[1]
1S
2 I/O
3S
4G
5I
6I
7G
8O
9G
Description
analog supply voltage
internally connected; leave open
analog supply voltage
analog ground
clock input
complementary clock input
analog ground
internally connected; leave open
digital ground
TDA9935_4
Product data sheet
Rev. 04 — 17 September 2007
© NXP B.V. 2007. All rights reserved.
3 of 18



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NXP Semiconductors
TDA9935www.DataSheet4U.com
Dual 14-bit, up to 160 Msample/s, 2 × interpolating DAC
TDA9935_4
Product data sheet
Table 2.
Symbol
VCCD
I13
I12
I11
I10
I9
I8
DGND
DEC
I7
I6
I5
I4
I3
I2
DGND
DEC
I1
I0
DGND
DGND
Q13
Q12
Q11
Q10
DGND
DEC
Q9
Q8
Q7
Q6
Q5
Q4
DEC
DGND
Q3
Q2
Q1
Q0
DGND
DGND
Pin description …continued
Pin Type[1] Description
10 S
digital supply voltage
11 I
I data input bit 13 (MSB)
12 I
I data input bit 12
13 I
I data input bit 11
14 I
I data input bit 10
15 I
I data input bit 9
16 I
I data input bit 8
17 G
digital ground
18 O
decoupling node
19 I
I data input bit 7
20 I
I data input bit 6
21 I
I data input bit 5
22 I
I data input bit 4
23 I
I data input bit 3
24 I
I data input bit 2
25 G
digital ground
26 O
decoupling node
27 I
I data input bit 1
28 I
I data input bit 0 (LSB)
29 G
digital ground
30 G
digital ground
31 I
Q data input bit 13 (MSB)
32 I
Q data input bit 12
33 I
Q data input bit 11
34 I
Q data input bit 10
35 G
digital ground
36 O
decoupling node
37 I
Q data input bit 9
38 I
Q data input bit 8
39 I
Q data input bit 7
40 I
Q data input bit 6
41 I
Q data input bit 5
42 I
Q data input bit 4
43 O
decoupling node
44 G
digital ground
45 I
Q data input bit 3
46 I
Q data input bit 2
47 I
Q data input bit 1
48 I
Q data input bit 0
49 G
digital ground
50 G
digital ground
Rev. 04 — 17 September 2007
© NXP B.V. 2007. All rights reserved.
4 of 18




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