TCD2950D Datasheet PDF - Toshiba Semiconductor

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TCD2950D
Toshiba Semiconductor

Part Number TCD2950D
Description Image SensorCCD
Page 13 Pages


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Preliminary TOSHIBA CCD Image SensorCCD (charge coupled device)
TCD2950D
TCD2950D
The TCD2950D is a high sensitive and low dark current 10680
elements × 6 line CCD color image sensor which includes CCD
drive circuit and clamp circuit. The sensor is designed for
scanner.
The device contains a row of 10680 elements × 6 line staggered
photodiodes which provide a 96 lines/mm (2400DPI) across a A4
size paper. The device is operated by 5 V pulse, and 12 V power
supply.
Features
· Number of image sensing elements: 10680 elements × 6 line
Weight: 5.2 g (typ.)
· Image sensing element size: 2.8 µm by 4 mm on 4 µm centers
· Photo sensing region: High sensitive and low dark current PN photodiode
· Distance between photodiode array: 64 µm (16 lines)
· Clock: 2 phase (5 V)
· Power supply: 12 V power supply voltage
· Internal circuit: Clamp circuit
· Package: 22 pin CERDIP package
Pin Connections (top view)
· Color filter: Red, green, blue
OS3 1
22 OS2
Maximum Ratings (Note1)
Characteristics
Symbol
Rating
Clock pulse voltage
Shift pulse voltage
Reset pulse voltage
Clamp pulse voltage
Power supply voltage
Operating temperature
Storage temperature
VB
VSH
VRS
VCP
VOD
Topr
Tstg
-0.3~8.0
-0.3~15
0~60
-25~85
Note1: All voltage are with respect to SS terminals (ground).
Unit
V
V
°C
°C
SS 2
RS 3
SS 4
NC 5
f1A1 6
f2A1 7
f2A2 8
f1A2 9
SH3 10
SS 11
21 OS1
20 OD
19 CP
18 SS
17 f1A4
16 f2A4
15 f2A3
14 f1A3
13 SH1
12 SH2
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Circuit Diagram
OD CP SS
20 19 18
OS1 21
CLAMP
TCD2950D
f1A4 f2A4
17 16
f2A3 f1A3
15 14
CCD ANALOG SHIFT REGISTER 1
SHIFT GATE 1
PHOTO
DIODE
(B)
PHOTO
DIODE
(B)
SHIFT GATE 2
CCD ANALOG SHIFT REGISTER 2
13 SH1
OS2 22
CLAMP
CCD ANALOG SHIFT REGISTER 3
SHIFT GATE 3
PHOTO
DIODE
(G)
PHOTO
DIODE
(G)
SHIFT GATE 4
CCD ANALOG SHIFT REGISTER 4
12 SH2
OS3 1
SS
CLAMP
CCD ANALOG SHIFT REGISTER 5
SHIFT GATE 5
PHOTO
DIODE
(R)
PHOTO
DIODE
(R)
SHIFT GATE 6
CCD ANALOG SHIFT REGISTER 6
10 SH3
3 46 7
RS SS f1A1 f2A1
8 9 11
f2A2 f1A2 SS
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TCD2950D
Optical/Electrical Characteristics
(Ta = 25°C, VOD = 12 V, VB = VSH =V RS = V CP = 5 V (pulse), fB = 1 MHz, f RS = 2 MHz,
tINT = 11 ms, LIGHT SOURCE = A LIGHT SOURCE + CM500S FILTER (t = 1 mm),
LOAD RESISTANCE = 100 kW)
Characteristics
Symbol
Min Typ. Max
Unit
Note
Sensitivity
Red
Green
Blue
Photo response non uniformity
Register imbalance
Saturation Output Voltage
Saturation Exposure
Dark signal Voltage
Dark Signal Non Uniformity
DC Power Dissipation
Total Transfer Efficiency
Output Impedance
DC Compensation Output Voltage
Random Noise
Reset Noise
Masking Noise
R(R)
R(G)
R(B)
PRNU (1)
PRNU (3)
RI
VSAT
SE
VDRK
DSNU
PD
TTE
ZO
VOS
NDI
VRSN
VMS
0.9
1.3
0.9
¾
¾
¾
2.9
1.16
¾
¾
¾
92
¾
5.0
¾
¾
¾
1.4
1.9
1.3
15
3
1
3.5
1.84
0.5
2.0
420
98
0.3
6.0
0.8
0.3
0.2
1.9
2.5
1.7
20
12
¾
¾
¾
2.0
7.0
585
¾
1.0
7.0
¾
1.0
1.0
V/lxs (Note 2)
% (Note 3)
mV (Note 4)
% (Note 5)
V (Note 6)
lxs (Note 7)
mV (Note 8)
mV (Note 8)
mW ¾
%¾
kW ¾
V (Note 9)
mV (Note 10)
V (Note 9)
V (Note 9)
Note 2: Sensitivity is defined for each color of signal outputs average when the photosensitive surface is applied
with the light of uniform illumination and uniform color temperature.
Note 3: PRNU (1) is defined for each color on a single chip by the expressions below when the photosensitive
surface is applied with the light of uniform illumination and uniform color temperature.
PRNU (1) = ,x ´ 100 (%)
x
Where x is average of total signal output and DX is the maximum deviation from x .
The amount of incident light is shown below.
Red = 1/2·SE
Green = 1/2·SE
Blue = 1/4·SE
Note 4: PRNU (3) is defined as maximum voltage with next pixels, where measured at 5% of SE (typ.).
Note 5: Register imbalance is defined as follows.
21359
å xn - x (n + 1)
RI=
n =1
21359 ´ x 
 ´1 00 (%)
Note 6: VSAT is defined as minimum saturation output of all effective pixels.
Note 7: Definition of SE
SE =
VSAT
RG
(lxs)
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TCD2950D
Note 8: VDRK is defined as average dark signal voltage of all effective pixels.
DSNU is defined as different voltage between VDRK and VMDK when VMDK is maximum dark signal
voltage.
VMDK
VDRK
DSNU
Note 9: DC signal output voltage is defined as follows. Reset noise voltage is defined as follows.
Masking noise voltage is defined as follows.
OS VRSN
VOS
VMS
SS
Note 10: Random noise is defined as the standard deviation (sigma) of the output level difference between two
adjacent effective pixels under no illumination (i.e. darkconditions) calculated by the following procedure.
Output waveform
(effective pixels under
dark condition)
video output
200 ns
video output
200 ns
DV
pixel (n)
pixel (n + 1)
(1) Two adjacent pixels (pixel n and n + 1) in one reading are fixed as measurement points.
(2) Each of the output level at video output periods averaged over 200 ns period to get V (n) and V (n + 1).
(3) V (n + 1) is subtracted from V (n) to get DV.
DV = V (n) - V (n + 1)
(4) The standard deviation of DV is calculated after procedure (2) and (3) are repeated 30 times (30
readings).
DV
=
1
30
30
å|
i=1
Vi
|
I=
1
30
30
å (|
i=1
DVi
|DV )2
(5) Procedure (2), (3) and (4) are repeated 10 times to get sigma value.
(6) 10 sigma values are averaged.
I
=
1
10
10
åI
j=1
j
(7) I value calculated using the above procedure is observed 2 times larger than that measured
relative to the ground level. So we specify random noise as follows.
NDI = 1 I
2
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