TC58NVG2S0HBAI6 Datasheet PDF - Toshiba

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TC58NVG2S0HBAI6
Toshiba

Part Number TC58NVG2S0HBAI6
Description 4G-BIT (512M x 8 BIT) CMOS NAND E2PROM
Page 30 Pages


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TC58NVG2S0HBAI6
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
4 GBIT (512M × 8 BIT) CMOS NAND E2PROM
DESCRIPTION
The TC58NVG2S0HBAI6 is a single 3.3V 4 Gbit (4,563,402,752 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (4096 + 256) bytes × 64 pages × 2048blocks.
The device has two 4352-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 4352-byte increments. The Erase operation is implemented in a single block
unit (256 Kbytes + 16 Kbytes: 4352 bytes × 64 pages).
The TC58NVG2S0HBAI6 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
Memory cell array
Register
Page size
Block size
x8
4352 × 128K × 8
4352 × 8
4352 bytes
(256K + 16K) bytes
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read
Mode control
Serial input/output
Command control
Number of valid blocks
Min 2008 blocks
Max 2048 blocks
Power supply
VCC = 2.7V to 3.6V
Access time
Cell array to register 25 µs max
Serial Read Cycle
25 ns min (CL=50pF)
Program/Erase time
Auto Page Program
Auto Block Erase
300 µs/page typ.
2.5 ms/block typ.
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
30 mA max.
30 mA max
30 mA max
50 µA max
Package
P-VFBGA67-0608-0.80-001 (Weight: 0.095 g typ.)
8 bit ECC for each 512Byte is required.
1 2013-07-05C

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