TC518129BFWL-70V Datasheet PDF - Toshiba

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TC518129BFWL-70V
Toshiba

Part Number TC518129BFWL-70V
Description SILICON GATE CMOS PSEUDO STATIC RAM
Page 14 Pages


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TOSHIBA
TC5l8l29BPL/BFL/BFWL/BFIL-70V/80V/lOV
SILICON GATE CMOS
131,072 WORD x 8 BIT CMOS PSEUDO STATIC RAM
Description
The TC518129B-V is a 1M bit high speed CMOS pseudo static RAM organized as 131,072 words by 8 bits. The TC518129B-V
utilizes a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, high speed and low power
storage. The TC518129B-V operates from a single power supply of 2.7 - 5.5V. Refreshing is supported by a refresh (RFSf-i input
which enables two types of refreshing - auto refresh and self refresh. The TC518129B-V features a static RAM-like interface with a
write cycle in which the input data is written into the memory cell at the rising edge of RNV thus simplifying the microprocessor
interface.
A CS standby mode interface is incorporated in the TC518129B-V family, with the CE2 pin in the TC518128B-V family changed
to a CS pin. The TC518129B-V is available in a 32-pin, 0.6 inch width plastic DIP, a small outline plastic flat package, and a 32-pin thin
small outline plastic package (forward type).
Features
• Organization:
131,072 words x 8 bits
• Low voltage operation:
2. 7V - 5. 5V
• Data retention supply voltage: 2.7V - 5.5V
• Fast access time
TC518129B-V Family
crtCEA Access Time
tOEA N Access Time
tRC Cycle Time
Power Dissipation
Is.sv
Self Refresh Current
1 3.0V
-70
70ns
2Sns
115ns
38SmW
-80
80ns
30ns
130ns
330mW
SO/lA
2S/lA
-10
100ns
40ns
160ns
27SmW
• Auto refresh is supported by an internal refresh address
counter
• Self refresh is supported by an internal timer
• Inputs and outputs TTL compatible
• Refresh: 512 refresh cycles/8ms
• Auto refresh power down feature
• Package
- TC518129BPL-V: DIP32-P-600
- TC518129BFL-V: SOP32-P-450
- TC518129BFWL-V: SOP32-P-525
- TC518129BFTL-V: TSOP32-P-0820
Pin Connection (Top View)
RFSH
A16
A14
A12
A7
A6
AS
A4
A3
A2
Al
AO
1101
1102
1103
GNO
x~~
CS
Rom
A13
A8
A9 TC5l8129BFTL(FonNard)
A1l
OE
AlO
CE
1108
1101
1106
1105
1104
TCS191299Pl/BFl/BFVVl
Pin Names
AO - A16 Address Inputs
RIW ReadIWrite Control Input
OE Output Enable Input
'R'FSR
Refresh Input
CE Chip Enable Input
CS Chip Select Input
1/01 - 1/08 Data InputslOutputs
VDD
GND
Power
Ground
(TSOP)
PIN NO.
1
2
3 4 S6 7
8
9 10 11 12 13 14 1S 16
PIN NAME A11 Ag As A13 R/W CS A15 VDD R"F'SR A16 A14 A12 A7 Ae As A4
PIN NO. 17 18 19 20 21 22 23 24 2S 26 27 28 29 30 31 32
crPIN NAME A3 A2 A1 Ao 1/01 1/02 1/03 GND 1/04 I/OS 1/06 1/07 1/08
A10 N
TOSHIBA AMERICA ELECTRDNIC COMPONENTS. INC.
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TC51S129BPL/BFL/BFWLlBFTL-70V/SOV/10V
Block Diagram
Static RAM
ROW
ADDRESS
BUFFER (9)
CE
CS
MEMORY
ARRAY
512x256x8
1/01
1
I/OS
R!WO---CI
Operating Mode
~MODE
CE CS OE R/W RFSH AO -A16 1/01- 8
Read
Write
cr only Refresh
LHLH *
LH* L *
LHHH *
V* OUT
V* IN
V* HZ
CS Standby
Auto/Self Refresh
L L * * * * HZ
H * * * L * HZ
Standby
H * * * H * HZ
H = High level input (VIH)
L = Low level input (VIJ
* = VIH orVIL
V* = At the falling edge of CE, all address inputs are latched. At all other times, the address inputs are "*".
HZ = High impedance
Maximum Ratings
SYMBOL
ITEM
VIN Input Voltage
VOUT Output Voltage
Voo Power Supply Voltage
TOPR Operating Temperature
TSTRG Storage Temperature
TSOLOER Soldering Temperature· Time
Po Power Dissipation
lOUT Short Circuit Output Current
RATING
-1.0 -7.0
-1.0-7.0
-1.0 - 7.0
0-70
-55 - 150
260·10
600
50
UNIT NOTES
V
V
V
°C
°C
°C· sec
mW
1
mA
D-136
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Static RAM
TC518129BPLlBFLlBFWLlBFTL-70V/80V/10V
DC Recommended Operating Conditions
SYMBOL
PARAMETER
Voo Power Supply Voltage
VIH Input High Voltage
VIL Input Low Voltage
MIN. TYP. MAX. UNIT NOTES
4.5 5.0
5.5
V
-2.4 Voo + 1.0 V
-1.0 - 0.8 V
2
DC Characteristics (Ta = 0 - 700C, Voo = 5V±10%)
SYMBOL
PARAMETER
1000
100s1
100S2
100F1
100F2
100F3
100F4
II(L)
10(L)
VOH
VOL
Operating Current (Average)
cr, Address cycling: tRC = tRC min.
70ns version
80ns version
1OOns version
Standby Current
cr=VIH,~=VIH
Standby Current
cr = Voo - 0.2V, ~ = Voo - 0.2V
Self Refresh Current (Average)
cr=VIH, ~=VIL
Self Refresh Current (Average)
cr = Voo - 0.2V, 'RFSH = 0.2V
Auto Refresh Current (Average)
R'J!SH cycling: tFC = tFC min.
cr only Refresh Current (Average)
cr, Address cycling: tRC = tRC min.
70ns version
SOns version
1OOns version
Input Leakage Current
OV ~ VIN ~ Voo, All other Inputs not under test = OV
Output Leakage Current
Output Disabled (CE = VIH or OE = VIH or RIW = Vld,
OV ~ VOUT ~ Voo
Output High Level
10H = -1.0mA
Output Low Level
10L= 2.1mA
MIN. TYP. MAX. UNIT NOTES
- 50 70
- 40 60 mA 3,4
- 35 50
- - 1 mA
- 35 50 ~
- - 1 mA
- 35 50 ~
- - 2 mA
- 50 70
- 40 60 mA 3
- 35 50
- - ±10 ~
- - ±10 ~
2.4 - - V
- - 0.4 V
Capacitance* (Voo = 5V, Ta = 25°C, f = 1MHz)
SYMBOL
PARAMETER
CI1 Input Capacitance (AO - A16)
CI2 Input Capacitance (cr, CS, OE, RIW, ~)
CIO Input/Output Capacitance
*This parameter is periodically sampled and is not 100% tested.
MIN. MAX. UNIT
-5
- 7 pF
-7
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TC518129BPUBFUBFWUBFTL-70V/80V/10V
Static RAM
AC Characteristics (Ta = 0 - 700C, Vee =5V±10%) (Notes: 5, 6, 7, 8)
SYMBOL
PARAMETER
tRC
tRMW
tCE
tp
tCEA
tOEA
tClZ
tOll
tWlZ
tCHz
tOHZ
tWHZ
taos
tooH
tRCS
tRCH
tcss
tCSH
twp
tWCH
tCWl
tosw
tosc
tOHW
toHC
tASC
tAHC
tRHC
tFC
tRFO
tFAP
tFP
tFAS
tFRS
tREF
tT
Random Read, Write Cycle Time
Read Modify Write Cycle Time
cr Pulse Width
cr Precharge Time
cr Access Time
'O't: Access Time
cr to Output in Low -Z
'O't: to Output in Low -Z
Output Active from End of Write
Chip Disable to Output in High-Z
'O't: Disable to Output in High-Z
Write Enable to Output in High-Z
'O't: Output Disable Setup Time
OE Output Disable Hold Time
Read Command Setup Time
Read Command Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Pulse Width
Write Command Hold Time
crWrite Command to Lead Time
Data Setup Time from RIW
Data Setup Time from CE
Data Hold Time from R!W
crData Hold Time from
Address Setup Time
Address Hold Time
'FWSH Command Hold Time
Auto Refresh Cycle Time
crRl=SR Delay Time from
Rl=SR Pulse Width (Auto Refresh)
'FWSH Precharge Time
Rl=SR Pulse Width (Self Refresh)
cr Delay Time from RFSR (Self Refresh)
Refresh Period (512 cycles, AO - A8)
Transition Time (Rise and Fall)
·70 ·80
MIN.
115
160
70
35
-
-
20
0
0
0
0
0
0
10
0
0
0
20
20
35
20
15
15
0
0
0
20
15
115
35
30
30
8,000
160
-
3
MAX.
-
-
10,000
-
70
25
-
-
-
20
20
25
-
-
-
-
-
-
-
10,000
10,000
-
-
--
-
-
-
-
-
-
8,000
-
-
-
8
50
MIN.
130
180
80
40
-
-
20
0
0
0
0
0
0
10
0
0
0
25
25
40
25
20
20
0
0
0
25
15
130
40
30
30
8,000
160
-
3
MAX.
-
-
10,000
-
80
30
-
-
-
20
20
25
-
-
-
-
-
-
-
10,000
10,000
-
-
-
-
-
-
-
-
-
8,000
-
-
-
8
50
·10
MIN.
160
220
100
50
-
-
20
0
0
0
0
0
0
10
0
0
0
30
30
50
30
25
25
0
0
0
30
15
160
50
30
30
8,000
190
-
3
MAX.
-
-
10,000
-
100
40
-
-
-
25
25
30
-
-
-
-
-
-
-
10,000
10,000
-
-
-
-
-
-
-
-
-
8,000
-
-
-
8
50
UNIT NOTES
I----
I----
I----
I----
I----
I----
I----
t---
I----
9
I----
9
I----
9
I----
I----
t---
I----
r-------:
ns I----
I----
I----
I----
I----
10
I----
10
I----
10
t---
10
I----
11
I----
11
I----
I----
I----
t---
12
I----
12
I----
12
I----
12
ms
ns
D-138
TOSHIBA AMERICA ELECTRONIC COMPDNENTS. INC.



TC518129BFWL-70V datasheet pdf
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