TC518129APL-12LV Datasheet PDF - Toshiba

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TC518129APL-12LV
Toshiba

Part Number TC518129APL-12LV
Description SILICON GATE CMOS PSEUDO STATIC RAM
Page 14 Pages


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TOSHIBA
TC5I8I29APLIAFLIAFWL-80LVII0LVI I2LV
TC5I8I29AF1L-80LVII0LVI I2LV
SILICON GATE CMOS
131,072 WORD x 8 BIT CMOS PSEUDO STATIC RAM
Description
The TC518129A-LV is a 1M bit high speed CMOS pseudo static RAM organized as 131,072 words by 8 bits. The TC518129A-LV
utilizes a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, high speed and low power
storage. The TC518129A-LV operates from a single power supply of 3.135V - 5.5V Refreshing is supported by a refresh (RFSro
input which enables two types of refreshing - auto refresh and self refresh. The TC518129A-LV features a static RAM-like interface
with a write cycle in which the input data is written into the memory cell at the rising edge of RIW thus simplifying the microproces-
sor interface.
A CS standby mode interface is incorporated in the TC518129A-LV family, with the CE2 pin in the TC518128A-LV family changed
to a CS pin. The TC518129A-LV is available in a 32-pin, 0.6 inch width plastic DIP, a small outline plastic flat package, and a 32-pin
thin small outline plastic package (forward type).
Features
• Organization:
131,072 words x 8 bits
• Low voltage operation:
3.135V - 5.5V
• Data retention supply voltage: 3.0V - 5.5V
• Fast access time
TC518129A-LV Family
-80 -10 -12
tCEA'CE Access Time
toEA OE Access Time
tRC Cycle Time
Power Dissipation
Is.sV
Self Refresh Current
1 3.0V
80ns
3Sns
130ns
38SmW
100ns
40ns
160ns
330mW
200~
100~
120ns
SOns
190ns
27SmW
• Auto refresh is supported by an intemal refresh address counter
• Self refresh is supported by an internal timer
• Inputs and outputs TIL compatible
• Refresh: 512 refresh cycles/8ms
• Auto refresh power down feature
• Package
- TC518129APL: DIP32-P-600
- TC518129AFL: SOP32-P-450
- TC518129AFWL: SOP32-P-525
- TC518129AFTL: TSOP32-P-0820
Pin Connection (Top View)
RFSH
A16
A14
Al2
A7
A6
AS
A4
A3
A2
Al
AO
1/01
1/02
1103
GND
Voo
AIS
CS
R/IN
All
A8
A9
Al'
OE
Al0
CE
1108
1107
1106
1/05
1104
res I 8129APL I AFL I AFWL
TCS18129AFTL ( Forward)
Pin Names
AO -A16
R!W
OE
RJ!SR
'CE
CS
1/01 - 1/08
Voo
GND
Address Inputs
Read/Write Control Input
Output Enable Input
Refresh Input
Chip Enable Input
Chip Select Input
Data InputslOutputs
Power
Ground
(TSOP)
PIN NO.
1
2
3 4S6 7 8
9 10 11 12 13 14 1S 16
PIN NAME A11 Ag As A13 R!W CS A15 Voo RJ!SR A16 A14 A12 A7 As A5 A4
PIN NO. 17 18 19 20 21 22 23 24 2S 26 27 28 29 30 31 32
PIN NAME A3 A2 A1 Ao 1/01 1/02 1/03 GND 1/04 I/OS 1/06 1/07 1/08 'CE A10 OE
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TC518129APLlAFL/AFWLlAFTL·80LV/10LV/12LV Static RAM
Block Diagram
ROW
ADDRESS
BUFFER (9)
CE
CS
MEMORY
ARRAY
512)(256)(8
R/Wo---oQ
Operating Mode
~NMOOE
CE CS OE R/W RFSH AO -A16 1/01 - 8
Read
Write
cr only Refresh
CS Standby
Auto/Self Refresh
Standby
LHL H *
LH * L *
LHH H *
LL * * *
H* * * L
H* * * H
V* OUT
V* IN
V* HZ
* HZ
* HZ
* HZ
H = High level input (VIH)
L =Low level input (VII)
* = VIH orVIL
V* = At the falling edge of CE, all address inputs are latched. At all other times, the address inputs are" *".
HZ = High impedance
Maximum Ratings
SYMBOL
ITEM
VIN Input Voltage
VOUT Output Voltage
Voo Power Supply Voltage
TOPR Operating Temperature
TSTRG Storage Temperature
TSOLOER Soldering Temperature • Time
Po Power DisSipation
lOUT Short Circuit Output Current
RATING
-1.0 -7.0
-1.0 -7.0
-1.0 -7.0
0-70
-55 - 150
260·10
600
50
UNIT
V
V
V
°C
°C
°C· sec
mW
mA
NOTES
1
0·102
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Static RAM TC518129APUAFUAFWUAFTL-80LV/1 OLVl12LV
DC Recommended Operating Conditions
SYMBOL
PARAMETER
Voo Power Supply Voltage
VIH Input High Voltage
VIL Input Low Voltage
MIN. TYP. MAX. UNIT NOTES
4.5 5.0
5.5
V
2.4 - Voo + 1.0 V
-1.0 - 0.8 V
2
= =DC Characteristics (Ta 0 - 700C, Voo 5V±10%)
SYMBOL
PARAMETER
Operating Current (Average)
1000 'C"E', Address cycling: tRC = tRC min.
80ns version
1OOns version
120ns version
100S1
100S2
100F1
100F2
Standby Current
'C"E' = VIH ,'R'F'SH = V1H
Standby Current
'C"E' = Voo - 0.2V,
'R'F'SH = Voo - 0.2V
Self Refresh Current (Average)
'C"E' = VIH,
'R'F'SH = VIL
Self Refresh Current (Average)
'C"E' = Voo - 0.2V,
'R'F'SH = 0.2V
Auto Refresh Current (Average)
100F3 'R'F'SH cycling: tFC = tFC min
'C"E' only Refresh Current (Average)
100F4 'CE, Address cycling: tRC = tRC min.
80ns version
1OOns version
120ns version
Input Leakage Current
II(L) OV ~ VIN ~ Voo, All other Inputs not under test = OV
Output Leakage Current
10(L) Output Disabled ('C"E' = VIH or'OE' = VIH or RIW = Vld,
OV ~ Your ~ Voo
VOH
Output High Level
10H = -SmA
Output Low Level
VOL 10L= 4.2mA
MIN. TYP. MAX. UNIT NOTES
- 50 70
- 40 60 mA 3,4
- 35 50
- - 1 mA
- 100 200 !lA
- - 1 mA
- 100 200 !lA
- - 2 mA
- 50 70
- 40 60 mA
- 35 50
- - ±10 !lA
- - ±10 !lA
2.4 -
--
-V
0.4 V
3
= = =Capacitance* (Voo 5Y, Ta 25°C, f 1MHz)
SYMBOL
PARAMETER
CI1 Input Capacitance (AO ~ A16)
CI2 Input Capacitance ('CE, CS, 'OE', RIW, R"FSH)
CIO Input/Output Capacitance
*This parameter is periodically sampled and is not 100% tested.
MIN. MAX. UNIT
-5
- 7 pF
-7
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TC518129APLIAFL/AFWL/AFTL-80LV/10LV/12LV Static RAM
AC Characteristics (Ta =0 - 70°C, Voo =5V±10%) (Notes: 5, 6, 7, 8)
SYMBOL
PARAMETER
-80
MIN. MAX.
-10
MIN. MAX.
tRC
tRMW
tCE
tp
tCEA
toEA
tCLZ
toLZ
tWLZ
tCHZ
toHZ
tWHZ
toos
toOH
tRCS
tRCH
tcss
tCSH
twp
tWCH
tCWL
tosw
tosc
tOHW
tOHC
tASC
tAHC
tRHC
tFC
tRFO
tFAP
tFP
tFAS
tFRS
tREF
tr
Random Read, Write Cycle Time
Read Modify Write Cycle Time
cr Pulse Width
cr Precharge Time
cr Access Time
OE Access Time
cr to Output in Low -Z
OE to Output in Low -Z
Output Active from End of Write
Chip Disable to Output in High-Z
OE Disable to Output in High-Z
Write Enable to Output in High-Z
OE Output Disable Setup Time
nE Output Disable Hold Time
Read Command Setup Time
Read Command Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Pulse Width
Write Command Hold Time
crWrite Command to Lead Time
Data Setup Time from R/W
Data Setup Time from CE
Data Hold Time from R/W
crData Hold Time from
Address Setup Time
Address Hold Time
~ Command Hold Time
Auto Refresh Cycle Time
cr~ Delay Time from
~ Pulse Width (Auto Refresh)
~ Precharge Time
~ Pulse Width (Self Refresh)
cr Delay Time from ~ (Self Refresh)
Refresh Period (512 cycles, AO - A8)
Transition Time (Rise and Fall)
130
195
80
40
-
-
30
0
0
0
0
0
0
10
0
0
0
20
60
60
60
30
30
0
0
0
20
15
130
40
30
30
8,000
160
-
3
-
-
10,000
-
80
35
-
-
-
25
25
25
-
-
-
-
-
-
-
10,000
10,000
-
-
-
-
-
-
-
-
-
8,000
-
-
-
8
50
160
235
100
50
-
-
30
0
0
0
0
0
0
10
0
0
0
25
70
70
70
35
35
0
0
0
25
15
160
50
30
30
8,000
190
.,...
3
-
-
10,000
-
100
40
-
-
-
30
30
30
-
-
-
-
-
-
-
10,000
10,000
-
-
-
-
-
-
-
-
-
8,000
-
-
-
8
50
-12
MIN.
190
280
120
60
-
-
30
0
0
0
0
0
0
10
0
0
0
30
85
85
85
45
45
0
0
0
30
15
190
60
30
30
8,000
225
-
3
MAX.
_.
-
10,000
-
120
50
-
-
-
35
35
35
-
-
-
-
-
-
-
10,000
10,000
-
-
-
-
-
-
-
-
-
8,000
-
-
-
8
50
UNIT NOTES
f-
f-
r---
f-
r---
f-
f-
r---
9
f-
9
f-
9
~
f-
f-
f-
~
ns -
-
------.,. .
-
-
10
-
10
-
10
-
--1-0--
- 11
- 11
f-
~
'----
12
r----
12
r---
12
f-
12
ms
ns
D-104
TDSHIBA AMERICA ELECTRDNIC CDMPDNENTS, INC.



TC518129APL-12LV datasheet pdf
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TC518129APL-12LV SILICON GATE CMOS PSEUDO STATIC RAM TC518129APL-12LV
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