ST62T94B8 Datasheet PDF - STMicroelectronics

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ST62T94B8
STMicroelectronics

Part Number ST62T94B8
Description 8-BIT HCMOS MCU
Page 26 Pages


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ST6294
8-BIT HCMOS MCU WITH
A/D CONVERTER, EEPROM & AUTO-RELOAD TIMER
PRELIMINARY DATA
3 to 6.0V Supply Operating Range
8 MHz Maximum Clock Frequency
-25 to +85°C Operating Temperature Range
Run, Wait & Stop Modes
5 different interrupt vectors
Look-up table capability in ROM
User ROM:
3868 bytes
Data ROM:
User selectable size
(in program ROM)
Data RAM:
128 bytes
EEPROM:
128 bytes
PDIP28, PSO28 packages
21 fully software programmable I/O as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull outputs
– Analog Inputs
8 I/O lines can sink up to 20mA for direct LED or
TRIAC driving
8 bit counter with a 7-bit programmable prescaler
(Timer1)
8 bit auto-reload timer with 7-bit programmable
prescaler (AR Timer)
Digital Watchdog
8 bit A/D Converter with up to 13 analog inputs
8 bit Synchronous Peripheral Interface (SPI)
On-chip clock oscillator (Quartz Crystal or Ce-
ramic)
Power-on Reset
Clock output
9 powerful addressing modes
The development tool of the ST6294 microcon-
trollers consists of the ST626x-EMU emulation
and development system connected via a stand-
ard RS232 serial line to an MS-DOS Personal
Computer
1
PDIP28
1
PSO28
(Ordering Information at the end of the datasheet)
October 1993
This is Preliminary Data from SGS-THOMSON. Details are subject to change without notice.
1/26



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ST6294
Figure 1. ST6294 Pin Configuration
PB0
PB1
TEST
PB2
PB3
PB4
PB5
ARTIMin / PB6
ARTIMout / PB7
Ain / PA0
VD D
VS S
Ain / PA1
Ain / PA2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 PC0 / Ain
27 PC1 / TIM1 / Ain
26 PC2 / Sin / Ain
25 PC3 / Sout / Ain
24 PC4 / SCK / Ain
23 CLKout
22 RESET
21 OSCout
20 OSCin
19 PA7 / Ain
18 PA6 / Ain
17 PA5 / Ain
16 PA4 / Ain
15 PA3 / Ain
VR0A1822
Figure 2. ST6294 Block Diagram
TEST
TEST
INTERRUPT
USER PROGRAM
ROM
3884 Bytes
DATA ROM
USER
SELECTABLE
DATA RAM
12 8 Bytes
DATA EEPROM
12 8 Bytes
CL Ko ut
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
OSCILLATOR
+
DIVIDER
8 BIT CORE
POWER
SUPPLY
RESET
LVI
OS Cin OSCou t VDD VS S
RESET
2/26
PORT A
PORT B
PORT C
TIMER 1
AUTORELOAD
TIMER
PA0 ..PA3
PA4..PA7 / Ain
PB0..PB3 / 20mA SINK
PB4..PB5 / 20mA SINK
PB6 / ARTIMin / 20mA SINK
PB7 / ARTIMout / 20mA SINK
PC0 / Ain
PC1 / TIM1 / Ain
PC2 / Sin / Ain
PC3 / Sout / Ain
PC4 / SCK / Ain
Ain = Analog Input
SERIAL PERIPHERAL
INTERFACE (SPI)
DIGITAL WATCHDOG
8 BIT
A/D CONVERTER
VR0A1823



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ST6294
GENERAL DESCRIPTION
The ST6294 microcontroller is member of the 8-bit
HCMOS ST62xx family, a series of devices oriented
to low-medium complexity applications. All ST62xx
members are based on a building block approach: a
common core is surrounded by a combination of on-
chip peripherals (macrocells).
The macrocells of the ST6294 are: the Timer pe-
ripheral that includes an 8-bit counter with a 7-bit
software programmable prescaler (Timer1), the 8-
bit Auto-reload Timer with 7 bit programmable
prescaler (AR Timer), the 8-bit A/D Converter with
up to 13 analog inputs (A/D inputs are alternate
functions of I/O pins), the Digital Watchdog (DWD)
and an 8-bit Serial synchronous Peripheral Inter-
face (SPI). In addition, these devices offer 128
bytes of EEPROM for non volatile data storage.
The ST6294 is a version of the ST6265 specifically
tailored to be used in telephone set applications.
The only difference is that a CKOUT pin is provided
instead of the NMI pin. For this reason this
datasheet only contains information relating to the
differences to the ST6265, and thus should be read
in conjunction with the ST6265 datasheet. The
ST62E94 EPROM version is available for prototypes
and low-volume production; also OTP version is
available.
PIN DESCRIPTION
VDD and VSS. Power is supplied to the MCU using
these two pins. VDD is power and VSS is the ground
connection.
OSCin and OSCout. These pins are internally
connected with the on-chip oscillator circuit. A
quartz crystal, a ceramic resonator or an external
clock signal can be connected between these two
pins in order to allow the correct operation of the
MCU with various stability/cost trade-offs. The fre-
quency at OSCin and OSCout is internally divided
by 1, 2 or 4 by a software controlled divider.The
OSCin pin is the input pin, the OSCout pin is the
output pin.
RESET. The active low RESET pin is used to re-
start the microcontroller to the beginning of its pro-
gram.
TEST. The TEST must be held at VSS for normal
operation (an internal pull-down resistor selects
normal operating mode if TEST pin is not con-
nected).
CKOUT. This clock pin outputs the oscillator fre-
quency divided by 2 (fOSC/2). This function can be
disabled by software to reduce power consump-
tion.
PC1/TIM1/Ain. This pin can be used as a Port C
I/O bit, as Timer 1 I/O pin or as analog input for the
on-chip A/D converter. If programmed to be the
Timer 1 pin, in input mode it is connected to the
prescaler and acts as external timer clock or as
control gate for the internal timer clock. In the out-
put mode the timer pin outputs the data bit when a
time out occurs.
To use this pin as Timer 1 output a dedicated bit in
the TIMER 1 Status/Control Register must be set.
To use this pin as input pin the I/O pin has to be
programmed as input. The analog mode should be
programmed to use the line as an analog input.
PB6/ARTIMin, PB7/ARTIMout. These pins are
either Port B I/O bits or the Input and Output pins of
the Auto-reload Timer. To be used as timer input
function PB6 has to be programmed as input with
or without pull-up. A dedicated bit in the AR TIMER
Mode Control Register sets PB7 as timer output
function.
PA0-PA7. These 8 lines are organized as one I/O
port (A). Each line may be configured under soft-
ware control as input with or without internal pull-
up resistor, interrupt generating input with pull-up
resistor, analog input, open-drain or push-pull out-
put.
PB0-PB3, PB4, PB5. These 6 lines are organized
as one I/O port (B). Each line may be configured
under software control as input with or without in-
ternal pull-up resistor, interrupt generating input
with pull-up resistor, open-drain or push-pull out-
put. In output mode these lines can also sink 20mA
for direct LED and TRIAC driving. The reset con-
figuration of PB0-PB3 can be selected by mask op-
tion (pull-up or high impedance).
PC0-PC4. These 5 lines are organized as one I/O
port (C). Each line may be configured under soft-
ware control as input with or without internal pull-
up resistor, interrupt generating input with pull-up
resistor, analog input for the A/D converter, open-
drain or push-pull output. PC2-PC4 can also be
used as respectively Data in, Data out and Clock
I/O pins for the on-chip SPI to carry the synchro-
nous serial I/O signals.
3/26



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ST6294
ST6294 DESCRIPTION
The ST6294 is a version of the ST6265 standard
device dedicated to telephone set application.
From a user point of view (with the following excep-
tions) the ST6294 product has exactly the same
software and hardware features as the ST6265.
NMI
There is no external NMI pin in the ST6294. Al-
though the ST6294 uses the standard ST62 core,
which includes the NMI function. The user program
therefore cannot place the ST62 in NMI mode.
However, NMI mode is the default mode at power
on or after a system reset generated by the watch-
dog or through the RESET pin. In these cases, the
user software must perform a RETI instruction to
exit from NMI mode to enable further interrupts
from other sources prior to any other instruction.
The ST6265 data sheet must therefore be read in
this respect.
CKOUT PIN
The CKOUT pin is a dedicated output pin which en-
ables a stabilized clock output to drive external cir-
cuits without any additional components. The clock
output can be disabled by software to reduce
power cosumption.
The output frequency is the oscillator frequency
(before the Oscillator Divider) divided by 2 (fOSC/ 2).
The CKOUT pin is enabled through bit CKOUTEN
of the Oscillator Control Register, at address DCh.
The CKOUT pin provides high drive current capa-
bility.
Note :
When enabled through the CKOUTEN bit, the
clock output increases the device overall power
consumption by around 200µA. It should therefore
be disabled when the lowest power consumption is
required.
Oscillator Control Register
Figure 3. Oscillator Control Register
OSCR
Oscillator Control Register
( DCh, Read/ Write )
D7 D6 D5 D4 D3 D2 D1 D0
Division Ratio Selection RS0
Division Ratio Selection RS1
Reserved
CKOUTEN
Unused
D7-D4. These bits are not used.
CKOUTEN. This bit, when cleared to zero, enables
the output of the oscillator frequency divided by 2
at pin CKOUT. When it is set to one, pin CKOUT is
held high. CKOUTEN is cleared on reset.
D2. Reserved. Must be kept low.
RS1-RS0. These bits select the division ratio of the
Oscillator Divider in order to generate the internal
frequency. The following selections are available:
RS1
0
0
1
1
RS0
0
1
0
1
Division Ratio
1
2
4
4
4/26



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