ST20TP2BX50S Datasheet PDF - ST Microelectronics

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ST20TP2BX50S
ST Microelectronics

Part Number ST20TP2BX50S
Description Programmable Transport IC
Page 30 Pages


ST20TP2BX50S datasheet pdf
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.com ST20-TP2®
eet4UPROGRAMMABLE TRANSPORT IC FOR DVB APPLICATIONS
taShFEATURES
as Enhanced 32-bit VL-RISC CPU
.D0 to 50 MHz processor clock
wfast integer/bit operations
wvery high code density
ws 8 Kbytes on-chip SRAM
2 PWM/
counter
ST20
CPU
200 Mbytes/s maximum bandwidth
s Programmable memory interface
m4 separately configurable regions
8/16/32-bits wide
osupport for mixed memory
.c2 cycle external access
support for page mode DRAM
support for MPEG decoders
Usupport for PCMCIA CA module
t4s Serial communications
OS-Link
2 Programmable UARTs (ASC)
e2 Synchronous serial interfaces (I2C)
es Vectored interrupt subsystem
Prioritized interrupts
h8 levels of preemption
S500 ns response time
s DMA engines/interfaces
ta2 MPEG decoder DMAs
2 SmartCard interfaces
aLink IC DMA interface
Section filter engine
.DDVB descrambler DMA
Block move DMA
Teletext interface (I/O)
wIEEE 1284/ Transport out DMA
s PWM/counter module
wTwo 8-bit PWM
wTwo 32-bit counters and capture registers
Parallel
input/output
1 OS-Link
2 UART
(ASC)
2 I2C
8 Kbytes
SRAM
EMI
Section
filter
engine
Interrupt
controller
Link IC
interface
DVB
de-
scrambler
Block
move
DMA
2 MPEG
decode
DMAs
2
SmartCard
interface
s Low power controller
mReal time clock
oWatchdog timer
.cs Programmable IO module
Us Professional toolset support
t4ANSI C compiler and libraries
eINQUEST advanced debugging tools
es Technology
h208 pin PQFP package
taS0.5 micron process technology
as JTAG Test Access Port
IEEE 1284
interface
Low power
controller
APPLICATIONS
s Set top terminals
www.DAugust 1997
The information in this datasheet is subject to change
(ASC)
Teletext
interface
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Contents
ST20-TP2
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 ST20-TP2 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Transport demultiplexing .................................................................................................................... 8
2.2 ST20-TP2 functional modules ............................................................................................................ 10
3 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Registers ............................................................................................................................................. 14
3.2 Processes and concurrency ............................................................................................................... 15
3.3 Priority ................................................................................................................................................. 17
3.4 Process communications .................................................................................................................... 18
3.5 Timers ................................................................................................................................................. 18
3.6 Traps and exceptions ......................................................................................................................... 19
4 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1 Interrupt vector table ........................................................................................................................... 26
4.2 Interrupt handlers ................................................................................................................................ 26
4.3 Interrupt latency .................................................................................................................................. 27
4.4 Preemption and interrupt priority ........................................................................................................ 27
4.5 Restrictions on interrupt handlers ....................................................................................................... 27
4.6 Interrupt configuration registers .......................................................................................................... 28
5 Interrupt level controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1 Interrupt level controller registers ....................................................................................................... 33
6 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1 Instruction cycles ................................................................................................................................ 35
6.2 Instruction characteristics ................................................................................................................... 36
6.3 Instruction set tables ........................................................................................................................... 37
7 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.1 System memory use ........................................................................................................................... 46
7.2 Boot ROM ........................................................................................................................................... 47
7.3 Internal peripheral space .................................................................................................................... 47
8 Memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.1 SRAM ................................................................................................................................................. 51
9 External memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.1 Pin functions ....................................................................................................................................... 53
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9.2 External bus cycles ............................................................................................................................. 57
9.3 EMI Configuration ............................................................................................................................... 63
9.4 EMI initialization .................................................................................................................................. 77
10 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.1 Reset and Analyse .............................................................................................................................. 79
10.2 Bootstrap ............................................................................................................................................ 80
11 Test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.1 Boundary scan description ................................................................................................................. 82
12 Clocks and low power controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
12.1 Clocks ................................................................................................................................................. 83
12.2 Low power control ............................................................................................................................... 83
12.3 Low power configuration registers ...................................................................................................... 85
12.4 Clocking .............................................................................................................................................. 88
13 Asynchronous serial controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
13.1 Operation ............................................................................................................................................ 93
13.2 Hardware error detection capabilities ................................................................................................. 96
13.3 Baud rate generation .......................................................................................................................... 96
13.4 Interrupt control ................................................................................................................................... 98
13.5 SmartCard mode specific operation ................................................................................................... 102
14 SmartCard interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
14.1 External interface ................................................................................................................................ 103
14.2 SmartCard clock generator ................................................................................................................. 104
15 I2C interfaces (SSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
15.1 High-speed synchronous serial controller ........................................................................................... 106
16 PWM and counter module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
16.1 External interface ................................................................................................................................ 116
16.2 PWM and counter control registers .................................................................................................... 116
17 Parallel input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
17.1 PIO Ports0-4 ....................................................................................................................................... 121
18 Serial link interface (OS-Link) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
18.1 OS-Link protocol ................................................................................................................................. 124
18.2 OS-Link speed .................................................................................................................................... 124
18.3 OS-Link connections ........................................................................................................................... 125
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19 Link IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
19.1 External interface ................................................................................................................................ 126
19.2 Link IC interface operation .................................................................................................................. 126
20 MPEG DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
20.1 External interface ................................................................................................................................ 128
20.2 MPEG DMA transfers ......................................................................................................................... 128
20.3 MPEG control registers ....................................................................................................................... 130
21 DVB decryption controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
21.1 Decrypting blocks of data ................................................................................................................... 132
21.2 Control registers ................................................................................................................................. 133
22 Block move DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
22.1 Moving blocks of data ......................................................................................................................... 134
22.2 Configuration register ......................................................................................................................... 134
23 Teletext interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
23.1 Teletext interface pins ......................................................................................................................... 135
23.2 Teletext data out ................................................................................................................................. 135
23.3 Teletext data in ................................................................................................................................... 137
23.4 Teletext interrupt control ..................................................................................................................... 137
23.5 Control registers ................................................................................................................................. 137
24 Section filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
24.1 Section filter configuration registers .................................................................................................... 141
24.2 DMA registers ..................................................................................................................................... 143
24.3 Section filtering operation ................................................................................................................... 147
25 IEEE 1284 port (PC parallel port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
25.1 1284 port pins ..................................................................................................................................... 150
25.2 1284 Port modes of operation ............................................................................................................ 151
25.3 1284 port control registers .................................................................................................................. 156
25.4 Signal Filtering .................................................................................................................................... 165
26 Configuration register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
27 Device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
27.1 PIO pins and alternate functions ......................................................................................................... 176
27.2 Interrupt assignments ......................................................................................................................... 178
28 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
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