SSM2122 Datasheet PDF - Analog Devices

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SSM2122
Analog Devices

Part Number SSM2122
Description (SSM2120 / SSM2122) Dynamic Range Processors/Dual VCA
Page 12 Pages


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a
FEATURES
0.01% THD at +10 dBV In/Out
100 dB VCA Dynamic Range
Low VCA Control Feedthrough
100 dB Level Detection Range
Log/Antilog Control Paths
Low External Component Count
APPLICATIONS
Compressors
Expanders
Limiters
AGC Circuits
Voltage-Controlled Filters
Noise Reduction Systems
Stereo Noise Gates
Dynamic Range
Processors/Dual VCA
SSM2120/SSM2122
FUNCTIONAL BLOCK DIAGRAM
V+
CURRENT
MIRRORS
SIGNAL
OUT
36k
–VC
+VC
V+
V+
SIGNAL
INPUT 36k
V+
IREF
GENERAL DESCRIPTION
The SSM2120 is a monolithic integrated circuit designed for the
purpose of processing dynamic signals in various analog systems
including audio. This “dynamic range processor” consists of two
VCAs and two level detectors (the SSM2122 consists of two
VCAs only). These circuit blocks allow the user to logarithmically
control the gain or attenuation of the signals presented to the
level detectors depending on their magnitudes. This allows the
compression, expansion or limiting of ac signals, some of the
primary applications for the SSM2120.
V–
PIN CONNECTIONS
22-Pin Plastic DIP
(P Suffix)
16-Pin Plastic DIP
(P Suffix)
THRESH 1 1
22 GND
LOG AV 1 2
21 V+
CONOUT 1 3
20 SIGOUT 2
SIGOUT 1 4
19 +VC2
+VC1 5 SSM2120 18 CFT 2
CFT 1 6 TOP VIEW 17 –VC2
–VC1 7 (Not to Scale) 16 SIGIN 2
SIGIN 1 8
15 RECIN 2
RECIN 1 9
14 CONOUT 2
IREF 10
13 LOG AV 2
V– 11
12 THRESH 2
GND 1
16 GND
SIGOUT 1 2
15 V+
+VC1 3
14 SIGOUT 2
CFT 1 4 SSM2122 13 +VC2
TOP VIEW
–VC1 5 (Not to Scale) 12 CFT 2
SIGIN 1 6
11 –VC2
IREF 7
10 SIGIN 2
V– 8
9 GND
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
Free Datasheet http://www.datasheet4u.com/



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SSM2120/SSM2122–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@VS = ؎15 V, TA = +25؇C, IREF = 200 A, +VC = –VC = GND (AV = 0 dB). 0 dB = 1 V rms
unless otherwise noted)
Parameter
Conditions
SSM2120/SSM2122
Min Typ
Max Units
POWER SUPPLY
Supply Voltage Range
Positive Supply Current
Negative Supply Current
±5
8
–6
± 18 V
10 mA
–8 mA
VCAs
Max ISIGNAL (In/Out)
Output Offset
Control Feedthrough (Trimmed)
Gain Control Range
Control Sensitivity
Gain Scale Factor Drift
Frequency Response
Off Isolation
Current Gain
THD (Unity-Gain)
Noise (20 kHz Bandwidth)
RIN = ROUT = 36 k, –30 dB AV 0 dB
Unity-Gain
Unity Gain or Less
At 1 kHz
+VC = –VC = 0 V
+10 dBV IN/OUT
RE: 0 dBV
± 300
–85
–0.5
± 325
±1
± 750
6
–3300
250
100
0.005
–80
± 350
±8
+40
+0.5
0.04
µA
µA
µV
dB
mV/dB
ppm/°C
kHz
dB
dB
%
dB
LEVEL DETECTORS (SSM2120 ONLY)
Detection Range
Input Current Range
Rectifier Input Bias Current
Output Sensitivity (At LOG AV Pin)
Output Offset Voltage
Frequency Response
IIN = 1 mA p-p
IIN = 10 µA p-p
IIN = 1 µA p-p
90
0.085
95
4
3
± 0.5
1000
50
7.5
2800
± 3.4
dB
µA p-p
nA
mV/dB
mV
kHz
CONTROL AMPLIFIERS (SSM2120 ONLY)
Input Bias Current
Output Drive (Max Sink Current)
Input Offset Voltage
± 85 ± 175 nA
5.0 7.5
mA
± 0.5 ± 4.2 mV
Specifications are subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Operating Temperature Range . . . . . . . . . . . . –10°C to +55°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Current into Any Pin . . . . . . . . . . . . . . . . . . 10 mA
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C
Package Type
θJA1
θJC
Units
16-Pin Plastic DIP (P)
22-Pin Plastic DIP (P)
86
70
10
7
°C/W
°C/W
Model
SSM2120
SSM2122
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
–10°C to +50°C 22-Pin Plastic DIP (N-22)
–10°C to +50°C 16-Pin Plastic DIP (N-16)
NOTE
1θJA is specified for worst case mounting conditions, i.e., θJA is specified for
device in socket for P-DIP.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SSM2120/SSM2122 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–2– REV. C



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+VC1
INPUT 1
SSM2122
OUTPUT 1
RECIN 1
–VC1 CFT 1
+VC2
INPUT 2
OUTPUT 2
RECIN 2
–VC2 CFT 2
2V
2V
SSM2120/SSM2122
FULL
WAVE
RECTIFIER
|IIN|
V+ THRESH 1
CONOUT 1
LOG AV 1
V–
FULL
WAVE
RECTIFIER
|IIN|
V+ THRESH 2
CONOUT 2
LOG AV 2
V–
Figure 1. SSM2120 Block Diagram
VOLTAGE-CONTROLLED AMPLIFIERS
The two voltage-controlled amplifiers are full Class A current
in/current out devices with complementary dB/V gain control
ports. The control sensitivities are +6 mV/dB and –6 mV/dB. A
resistor divider (attenuator) is used to adapt the sensitivity of an
external control voltage to the range of the control port. It is
best to use 200 or less for the attenuator resistor to ground.
VCA PERFORMANCE
Figures 2a and 2b show the typical THD and noise performance
of the VCAs over ±20 dB gain/attenuation. Full Class A operation
provides very low THD.
0.03
VCA INPUTS
The signal inputs behave as virtual grounds. The input current
compliance range is determined by the current into the reference
current pin.
0.01
REFERENCE PIN
The reference current determines the input and output current
compliance range of the VCAs. The current into the reference
pin is set by connecting a resistor to V+. The voltage at the
reference pin is about two volts above V– and the current will be
I REF
=
[(V +) – ((V – ) + 2 V
RREF
)]
The current consumption of the VCAs will be directly pro-
portional to IREF which is nominally 200 µA. The device will
operate at lower current levels which will reduce the effective
dynamic range of the VCAs. With a 200 µA reference current,
the input and output clip points will be ± 400 µA. In general:
ICLIP = ± 2 IREF
VCA OUTPUTS
The VCA outputs are designed to interface directly with the virtual
ground inputs of external operational amplifiers configured as
current-to-voltage converters. The outputs must operate at virtual
ground because of the output stage’s finite output impedance.
The power supplies and selected compliance range determines
the values of input and output resistors needed. As an example,
with ± 15 V supplies and ±400 µA maximum input and output
current, choose RIN = ROUT = 36 kfor an output compliance
range of ± 14.4 V. Note that the signal path through the VCA
including the output current-to-voltage converter is noninverting.
0.003
–20 –10 0 10
GAIN – dB
a. VCA THD Performance vs. Gain
(+10 dBV In/Out @ 1 kHz)
–70
20
–80
–90
–20 –10 0 10
GAIN – dB
20
b. VCA Noise vs. Gain (20 kHz Bandwidth)
Figure 2. Typical THD and Noise Performance
REV. C
–3–



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SSM2120/SSM2122
TRIMMING THE VCAs
The control feedthrough (CFT) pins are optional control feed-
through null points. CFT nulling is usually required in applications
such as noise gating and downward expansion. If trimming is
not used, leave the CFT pins open.
Trim Procedure
1. Apply a 100 Hz sine wave to the control point attenuator.
The signal peaks should correspond to the control voltages
which induce the VCAs maximum intended gain and at least
30 dB of attenuation.
2. Adjust the 50 kpotentiometer for the minimum
feedthrough.
(Trimmed control feedthrough is typically well under 1 mV rms
when the maximum gain is unity using 36 kinput and output
resistors.)
Applications such as compressor/limiters typically do not require
control feedthrough trimming because the VCA operates at
unity-gain unless the signal is large enough to initiate gain
reduction. In this case the signal masks control feedthrough.
This trim is ineffective for voltage-controlled filter applications.
LEVEL DETECTION CIRCUITS
The SSM2120 contains two independent level detection
circuits. Each circuit contains a wide dynamic range full-wave
rectifier, logging circuit and a unipolar drive amplifier. These
circuits will accurately detect the input signal level over a
100 dB range from 30 nA to 3 mA peak-to-peak.
LEVEL DETECTOR THEORY OF OPERATION
Referring to the level detector block diagram of Figure 3, the
RECIN input is an AC virtual ground. The next block imple-
ments the full-wave rectification of the input current. This
current is then fed into a logging transistor (Q1) whose pair
transistor (Q2) has a fixed collector current of IREF. The LOG
AV output is then:
V LOG
AV
=
kT
q
ln |IIRIENF|
With the use of the LOG AV capacitor the output is then the log
of the average of the absolute value of IIN.
(The unfiltered LOG AV output has broad flat plateaus with
sharp negative spikes at the zero crossing. This reduces the
“work” that the averaging capacitor must do, particularly at low
frequencies.)
Note: It is natural to assume that with the addition of the
averaging capacitor, the LOG AV output would become the
average of the log of the absolute value of IIN. However, since the
capacitor forces an ac ground at the emitter of the output
transistor, the capacitor charging currents are proportional to
the antilog of the voltage at the base of the output transistor.
Since the base voltage of the output transistor is the log of the
absolute value of IIN, the log and antilog terms cancel, so the
capacitor becomes a linear integrator with a charging current
directly proportional to the absolute value of the input current.
This effectively inverts the order of the averaging and logging
functions. The signal at the output therefore is the log of the
average of the absolute value of IIN.
USING DETECTOR PINS RECIN, LOGAV, THRESH AND
CONOUT
When applying signals to RECIN (rectifier input) an input series
resistor should be followed by a low leakage blocking capacitor
since RECIN has a dc voltage of approximately 2.1 V above
ground. Choose RIN for a ± 1.5 mA peak signal. For ± 15 V
operation this corresponds to a value of 10 k.
A 1.5 Mvalue of RREF from log average to –15 V will establish
a 10 µA reference current in the logging transistor (Q1). This
will bias the transistor in the middle of the detector’s dynamic
current range in dB to optimize dynamic range and accuracy.
The LOG AV outputs are buffered and amplified by unipolar
drive op amps. The 39 k, 1 kresistor network at the
THRESH pin provides a gain of 40.
An attenuator from the CONOUT (control output) to the
appropriate VCA control port establishes the control sensitivity.
Use 200 for the attenuator resistor to ground and choose
RCON for the desired sensitivity. Care should be taken to minimize
capacitive loads on the control outputs CONOUT. If long lines
or capacitive loads are present, it is best to connect the series
resistor RCON as closely to the CONOUT pin as possible.
DYNAMIC LEVEL DETECTOR CHARACTERISTICS
Figures 4 and 5 show the dynamic performance of the level
detector to a change in signal level. The input to the detector (not
shown) is a series of 500 ms tone bursts at 1 kHz in successive
10 dBV steps. The tone bursts start at a level of –60 dBV (with
RIN = 10 k) and return to –60 dBV after each successive 10 dB
step. Tone bursts range from –60 dBV to +10 dBV. Figure 4
shows the logarithmic level detector output. The output of the
detector is 3 mV/dB at LOG AV and the amplifier gain is 40
which yields 120 mV/dB. Thus, the output at CONOUT is seen
to increase by 1.2 V for each 10 dBV increase in input level.
1k39k
RIN RECIN
INPUT
2V
V+ THRESH
FULL
WAVE
RECTIFIER
|IIN|
IREF
Q2
Q1
CONOUT
LOG AV
V–
RCON
TO VC
200
CAV
RREF
V–
Figure 3. Level Detector
–4–
REV. C



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