SLG8SP513 Datasheet PDF - Silego Technology

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SLG8SP513
Silego Technology

Part Number SLG8SP513
Description Clock Synthesizer
Page 24 Pages


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SLG8SP513
Clock Synthesizer for Intel
Mobile PCI-Express Chipset
Features
• Low Power CK505 compatible clock synthesizer
• SLG8SP513 is a cost reduced CK505 with integrated volt-
age regulator for mobile applications
• Scalable Low Voltage VDD I/O (3.3V to 1.05V) to reduce
power consumption
• Low Power differential outputs with integrated series ter-
mination resistors (50 ohm resistor to GND and 33 ohm
series resistor not needed)
• Integrated CK_SSCD function to provide additional
Spread Spectrum support for GMCH
• CLK_REQ# inputs to support SRC clock power manage-
ment
• 64 pin QFN Package
Output Summary
• 2- differential CPU clock outputs @ 0.7V
• 1 - selectable differential CPU/SRC clock output @ 0.7V
• 1 - selectable differential DOT96/SRC clock output @ 0.7V
• 8 - differential Serial Reference Clock (SRC) clock outputs
@ 0.7V
• 1 - selectable LCDCLK/27M clock output
• 1 - single-ended 48MHz clock output @ 3.3V
• 6 - single-ended 33MHz clock outputs @ 3.3V
• 1 - single-ended 14.318MHz clock output @ 3.3V
Table 1. Frequency Select Table (FS_C, FS_B, FS_A)
FFF
SSS
___
CBA
000
001
010
011
100
101
110
111
CPU
(MHz)
266.6
133.3
200.0
166.6
333.3
100.0
400.0
SRC
(MHz)
100.0
100.0
100.0
100.0
100.0
100.0
100.0
PCI REF
(MHz) (MHz)
33.3 14.318
33.3 14.318
33.3 14.318
33.3 14.318
33.3 14.318
33.3 14.318
33.3 14.318
Reserved
DOT_
96
(MHz)
96.0
96.0
96.0
96.0
96.0
96.0
96.0
USB
(MHz)
48.0
48.0
48.0
48.0
48.0
48.0
48.0
Pin Configuration
(Top View)
Table 2. LCDCLK & 27M_SS Spread Spectrum Table
B1b5
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B1b3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B1b2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B1b1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Spread Spectrum %
Reserved
Reserved
-0.50% SS
-1.00% SS
-1.50% SS
-2.00% SS
-2.50% SS
Reserved
Reserved
Reserved
+/-0.25% SS
+/-0.50% SS
+/-0.75% SS
+/-1.00% SS
+/-1.25% SS
Reserved
VSS_REF
XTAL_OUT
XTAL_IN
VDD_REF
REF/FS_C/TEST_SEL
SDA
SCL
PCI_0/CLKREQ_A#
VDD_PCI
PCI_1/CLKREQ_B#
PCI_2
PCI_3
^PCI_4/SEL_LCDCLK#
PCIF_5/ITP_EN
VSS_PCI
VDD_48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SLG8SP513
48 SRC_6
47 SRC_6#
46 VDD_SRC
45 PCI_STOP#
44 CPU_STOP#
43 VDD_SRC_I/O
42 SRC_10#
41 SRC_10
40 SRC_11/CLKREQ_H#
39 SRC_11#/CLKREQ_G#
38 SRC_9#
37 SRC_9
36 VSS_SRC
35 SRC_4#
34 SRC_4
33 VDD_SRC_I/O
Table 3. SEL_LCDCLK# Input Functional Table
SEL_LCDCLK#
0
1
Pin 20/21
DOT_96 / DOT_96#
SRC_0 / SRC_0#
Pin 24/25
LCDCLK / LCDCLK#
27M / 27M_SS
^ This pin has internal pull-down to GND
64-Pin QFN
9.0 x 9.0mm body, 0.50mm pitch
Other brands and names may be claimed as the property of others
Silego Technology, Inc.
000-0084513-10
Rev 1.0
Revised July 24, 2007



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SLG8SP513
Pin Description
Pin #
Name
1 VSS_REF
2 XTAL_OUT
3 XTAL_IN
4 VDD_REF
5 REF/FS_C/TEST_S
EL
6 SDA
7 SCL
8 PCI_0/CLKREQ_A#
9 VDD_PCI
10 PCI_1/CLKREQ_B#
11 PCI_2
12 PCI_3
13 PCI_4/SEL_LCDCL
K#
14 PCIF_5/ITP_EN
15 VSS_PCI
16 VDD_48
17 USB/FS_A
18 VSS_48
19 VDD_I/O
20 SRC_0/DOT_96
21 SRC_0#/DOT_96#
22 VSS_I/O
23 VDD_PLL3
24 LCDCLK/27M
25 LCDCLK#/27M_SS
26 VSS_PLL3
27 VDD_PLL3_I/O
28 SRC_2
29 SRC_2#
30 VSS_SRC
Type
Description
GND Ground for outputs.
O, SE 14.318MHz crystal output.
I 14.318MHz crystal input.
PWR 3.3V power supply for outputs.
I/O, SE
14.318 reference clock output.
When FS_C/TEST_SEL input is pulled to 3.3V during CKPWRGD assertion, the
device will configure into TEST MODE. Refer to DC Parameters section for FS
input voltage threshold. After CKPWRGD assertion, this pin will be configured as
REF output.
I/O, SE Serial Interface bus data input and output.
I Serial Interface bus clock input.
I/O, SE Configurable PCI clock output or CLKREQ input.
PWR 3.3V power supply for outputs.
I/O, SE Configurable PCI clock output or CLKREQ input.
O, SE PCI clock output.
O, SE PCI clock output.
I/O, SE
PCI clock output.
3.3V input to select output function of pin 20/21 and 24/25.
0 = LCDCLK & DOT_96 for internal graphic controller support
1 = 27M & 27M_SS & SRC_0 for external graphic controller support
I/O, SE
Free running PCI clock output.
When ITP_EN input is sampled HIGH during CKPWRGD assertion, it will config-
ure CPU_ITP/SRC_8 as CPU output.
GND Ground for outputs.
PWR 3.3V power supply for outputs.
I/O, SE USB clock output.
Frequency Select input to determine CPU output frequency.
GND Ground for outputs.
PWR Low voltage I/O power supply for outputs.
O, DIF Configurable SRC or 96 MHz DOT clock output.
O, DIF Configurable SRC or 96 MHz DOT clock output.
GND Ground for outputs.
PWR 3.3V power supply for outputs.
O, DIF/SE Clock output for graphic contoller.
O, DIF/SE Clock output for graphic contoller.
GND Ground for outputs.
PWR Low voltage I/O power supply for outputs.
O, DIF Configurable Serial Reference clock for SATA or PCI Express device.
O, DIF Configurable Serial Reference clock for SATA or PCI Express device.
GND Ground for outputs.
000-0084513-10
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SLG8SP513
Pin Description (continued)
Pin #
31
Name
SRC_3/CLKREQ_C
#
Type
I/O
32 SRC_3#/CLKREQ_
D#
I/O
33 VDD_SRC_I/O
34 SRC_4
PWR
O, DIF
35 SRC_4#
36 VSS_SRC
O, DIF
GND
37 SRC_9
O, DIF
38 SRC_9#
39 SRC_11#/CLKREQ_
G#
O, DIF
I/O
40 SRC_11/CLKREQ_H
#
I/O
41 SRC_10
42 SRC_10#
O, DIF
O, DIF
43 VDD_SRC_I/O
44 CPU_STOP#
PWR
I
45 PCI_STOP#
46 VDD_SRC
I
PWR
47 SRC_6#
O, DIF
48 SRC_6
49 VSS_SRC
O, DIF
GND
50 SRC_7#/CLKREQ_
E#
51 SRC_7/CLKREQ_F#
I/O
I/O
52 VDD_SRC_I/O
PWR
53 SRC_8#/CPU_ITP# O, DIF
54 SRC_8/CPU_ITP
O, DIF
55 NC
56 VDD_CPU_I/O
57 CPU_1_MCH#
58 CPU_1_MCH
59 VSS_CPU
60 CPU_0#
I
PWR
O, DIF
O, DIF
GND
O, DIF
Description
Configurable differential SRC clock output or CLKREQ input.
Configurable differential SRC clock output or CLKREQ input.
Low voltage I/O power supply for outputs.
Differential Serial Reference Clock output.
Differential Serial Reference Clock output.
Ground for outputs.
Differential Serial Reference Clock output.
Differential Serial Reference Clock output.
Configurable differential SRC clock output or CLKREQ input.
Configurable differential SRC clock output or CLKREQ input.
Differential Serial Reference Clock output.
Differential Serial Reference Clock output.
Low voltage I/O power supply for outputs.
3.3V LVTTL input for CPU_STOP#.
3.3V LVTTL input for PCI_STOP#.
3.3V power supply for outputs.
Differential Serial Reference Clock output.
Differential Serial Reference Clock output.
Ground for outputs.
Configurable differential SRC clock output or CLKREQ input.
Configurable differential SRC clock output or CLKREQ input.
Low voltage I/O power supply for outputs.
Selectable differential CPU or SRC output. It will configure as CPU clock when
ITP_EN is sampled HIGH. It will configure as SRC clock when ITP_EN is sam-
pled LOW.
Selectable differential CPU or SRC output. It will configure as CPU clock when
ITP_EN is sampled HIGH. It will configure as SRC clock when ITP_EN is sam-
pled LOW.
No connect.
Low voltage I/O power supply for outputs.
Differential CPU Clock output. This CPU output will be active during Intel AMT
M1 mode.
Differential CPU Clock output. This CPU output will be active during Intel AMT
M1 mode.
Ground for outputs.
Differential CPU Clock output.
000-0084513-10
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SLG8SP513
Pin Description (continued)
Pin #
Name
61 CPU_0
Type
O, DIF
62 VDD_CPU
63 CKPWRGD/PD#
PWR
I
64 FS_B/TEST_MODE
I
Description
Differential CPU Clock output.
3.3V power supply for outputs.
CKPWRGD is a 3.3V LVTTL iput. It acts as a level sensitive strobe to latch the
FS pins and other multiplexed inputs. After CKPWRGD assertion, it becomes a
real time input for asserting power down (active high).
Frequency Select input to determine CPU output frequency.
When in test mode, FS_B/TEST_MODE will configure outputs to run at REF or
Hi-Z. 0 = Hi-Z, 1 = REF
000-0084513-10
Page 4 of 24



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