SI591 Datasheet PDF - Silicon Laboratories


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SI591
Silicon Laboratories

Part Number SI591
Description (SI590 / SI591) 1 ps MAX JITTER CRYSTAL OSCILLATOR
Page 12 Pages

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Si590/591
1 ps MAX JITTER CRYSTAL OSCILLATOR (XO)
(10 MHZ TO 525 MHZ)
Features
Available with any-rate output
Available CMOS, LVPECL,
frequencies from 10 MHz to 525 MHz LVDS, and CML outputs
3rd generation DSPLL® with superior 3.3, 2.5, and 1.8 V supply options
jitter performance: 1 ps max jitter Industry-standard 5 x 7 mm
Better frequency stability than SAW- package and pinout
based oscillators
Pb-free/RoHS-compliant
Internal fundamental mode crystal –40 to +85 ºC operating
ensures high reliability
temperature range
Applications
SONET/SDH (OC-3/12/48)
Networking
SD/HD SDI/3G SDI video
Test and measurement
Storage
FPGA/ASIC clock generation
Description
The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL® circuitry
to provide a low jitter clock at high frequencies. The Si590/591 is available
with any-rate output frequency from 10 to 525 MHz. Unlike a traditional XO,
where a unique crystal is required for each output frequency, the Si590/591
uses one fixed crystal to provide a wide range of output frequencies. This IC
based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis provides
superior supply noise rejection, simplifying the task of generating low jitter
clocks in noisy environments typically found in communication systems. The
Si590/591 IC based XO is factory configurable for a wide variety of user
specifications including frequency, supply voltage, output format, and
temperature stability. Specific configurations are factory programmed at time
of shipment, thereby eliminating long lead times associated with custom
oscillators.
Functional Block Diagram
Si5602
Ordering Information:
See page 6.
Pin Assignments:
See page 5.
(Top View)
NC 1
6 VDD
OE 2
5 CLK–
GND 3
4 CLK+
Si590 (LVDS/LVPECL/CML)
OE 1
NC 2
6 VDD
5 NC
VDD CLK– CLK+
GND 3
4 CLK
17 k*
Any-rate
Fixed
10–525 MHz
OE
Frequency
DSPLL®
XO Clock
Synthesis
17 k*
GND
*Note: Output Enable High/Low Options Available – See Ordering Information
Si590 (CMOS)
OE 1
6 VDD
NC 2
5 CLK–
GND 3
4 CLK+
Si591 (LVDS/LVPECL/CML)
Preliminary Rev. 0.25 7/09
Copyright © 2009 by Silicon Laboratories
Si590/591
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Si590/591
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol Test Condition Min Typ Max Units
Supply Voltage1
VDD 3.3 V option
2.5 V option
2.97 3.3 3.63
2.25 2.5 2.75 V
1.8 V option
1.71 1.8 1.89
Supply Current
IDD Output enabled
LVPECL
— 110 125
CML
LVDS
— 100 110
— 90 100 mA
CMOS
— 80 90
Tristate mode — 60 75
Output Enable (OE)2
VIH
0.75 x VDD
V
VIL — — 0.5
Operating Temperature Range
TA
–40 — 85 ºC
Notes:
1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 6 for further details.
2. OE pin includes an internal 17 kpullup resistor to VDD for output enable active high or a 17 kpull-down resistor to
GND for output enable active low. See 3. "Ordering Information" on page 6.
Table 2. CLK± Output Frequency Characteristics
Parameter
Symbol
Test Condition
Min Typ Max Units
Nominal Frequency1,2
fO
LVPECL/LVDS/CML
10 — 525
MHz
CMOS
10 — 160
Initial Accuracy
fi
Measured at +25 °C at time of
shipping
±1.5
ppm
Total Stability
Note 3, second option code “C” —
— ±30 ppm
Note 4, second option code “B” —
— ±50 ppm
Note 4, second option code “A” —
— ±100 ppm
second option code “C”
— — ±20 ppm
Temperature Stability
second option code “B”
— — ±25 ppm
second option code “A”
— — ±50 ppm
Powerup Time5
tOSC
— — 10 ms
Notes:
1. See Section 3. "Ordering Information" on page 6 for further details.
2. Specified at time of order by part number.
3. Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 10 years aging at 40 °C. See
3. "Ordering Information" on page 6.
4. Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 15 years aging at 70 °C. See
3. "Ordering Information" on page 6.
5. Time from powerup or tristate mode to fO.
2 Preliminary Rev. 0.25
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Si590/591
Table 3. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option1
LVDS Output Option2
Symbol
VO
VOD
VSE
VO
Test Condition
mid-level
swing (diff)
swing (single-ended)
mid-level
Min
VDD – 1.42
1.1
0.55
1.125
Typ
1.20
Max Units
VDD – 1.25
1.9
0.95
V
VPP
VPP
1.275
V
VOD swing (diff)
0.5 0.7 0.9
CML Output Option2
VO
mid-level
— VDD – 0.75 —
CMOS Output Option3
VOD
VOH
swing (diff)
0.70
0.8 x VDD
0.95
1.20
VDD
VOL — — 0.4
Rise/Fall time (20/80%)
tR, tF
LVPECL/LVDS/CML
— 350
CMOS with CL = 15 pF
2
Symmetry (duty cycle)
SYM LVPECL: VDD – 1.3 V (diff)
LVDS: 1.25 V (diff)
45
CMOS: VDD/2
Notes:
1. 50 to VDD – 2.0 V.
2. Rterm = 100 (differential).
3. CL = 15 pF. Sinking or sourcing 12 mA for VDD = 3.3 V, 6 mA for VDD = 2.5 V, 3 mA for VDD = 1.8 V.
55
VPP
V
VPP
V
ps
ns
%
Table 4. CLK± Output Phase Jitter
Parameter
Symbol Test Condition Min Typ Max Units
Phase Jitter (RMS)1
for 50 MHz < FOUT < 525 MHz
(LVPECL/LVDS/CML)
Phase Jitter (RMS)2
for 50 MHz < FOUT < 160 MHz
(CMOS)
J 12 kHz to 20 MHz — 0.5 1.0 ps
J 12 kHz to 20 MHz — 0.6 1.0 ps
Notes:
1. Differential Modes LVPECL/LVDS/CML. 3.3 and 2.5 V supply voltage options only.
2. Single-ended CMOS output phase jitter measured using 33 series termination into 50 phase noise test equipment.
3.3 V supply voltage option only.
Table 5. CLK± Output Period Jitter
Parameter
Symbol
Test Condition
Min Typ Max Units
Period Jitter*
JPER
RMS
Peak-to-Peak
——
3 ps
— — 35
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Preliminary Rev. 0.25
3
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Si590/591
Table 6. Absolute Maximum Ratings1
Parameter
Symbol
Rating
Units
Maximum Operating Temperature
TAMAX
85
ºC
Supply Voltage, 1.8 V Option
VDD –0.5 to +1.9
V
Supply Voltage, 2.5/3.3 V Option
VDD –0.5 to +3.8
V
Input Voltage (any input pin)
VI
–0.5 to VDD + 0.3
Volts
Storage Temperature
TS –55 to +125 ºC
ESD Sensitivity (HBM, per JESD22-A114)
ESD
2500
V
Soldering Temperature (Pb-free profile)2
Soldering Temperature Time @ TPEAK (Pb-free profile)2
TPEAK
tP
260
20–40
ºC
seconds
Notes:
1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO for further information, including soldering profiles.
Table 7. Environmental Compliance
The Si590/591 meets the following qualification test requirements.
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross & Fine Leak
Resistance to Solvents
Conditions/Test Method
MIL-STD-883G, Method 2002.3 B
MIL-STD-883G, Method 2007.3 A
MIL-STD-883G, Method 203.8
MIL-STD-883G, Method 1014.7
MIL-STD-883G, Method 2015
4 Preliminary Rev. 0.25
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