SG3525A Datasheet PDF - STMicroelectronics


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SG3525A
STMicroelectronics

Part Number SG3525A
Description REGULATING PULSE WIDTH MODULATORS
Page 12 Pages

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SG2525A
® SG3525A
REGULATING PULSE WIDTH MODULATORS
. 8 TO 35 V OPERATION
. 5.1 V REFERENCE TRIMMED TO ± 1 %
. 100 Hz TO 500 KHz OSCILLATOR RANGE
. SEPARATE OSCILLATOR SYNC TERMINAL
. ADJUSTABLE DEADTIME CONTROL
. INTERNAL SOFT-START
. PULSE-BY-PULSE SHUTDOWN
. INPUT UNDERVOLTAGE LOCKOUT WITH
HYSTERESIS
. LATCHING PWM TO PREVENT MULTIPLE
PULSES
. DUAL SOURCE/SINK OUTPUT DRIVERS
DIP16
16(Narrow)
DESCRIPTION
The SG3525Aseries of pulse width modulator inte-
grated circuits are designed to offer improved per-
formance and lowered external parts count when
used in designing all types of switching power sup-
plies. The on-chip + 5.1 V reference is trimmed to ±
1 % and the input common-mode range of the error
amplifier includes the reference voltage eliminating
external resistors. A sync input to the oscillator al-
lows multiple units to be slaved or a single unit to be
synchronized to an external system clock. A single
resistor betweenthe CT andthe dischargeterminals
provide a wide range of dead time ad- justment.
Thesedevicesalso featurebuilt-insoft-startcircuitry
with only an external timing capacitor required. A
shutdownterminal controls both the soft-start circu-
ity and the output stages, providing instantaneous
turn off through the PWM latch with pulsed shut-
down, as well as soft-start recycle with longer shut-
down commands. These functions are also control-
led by an undervoltagelockoutwhich keepsthe out-
puts off and the soft-start capacitor discharged for
sub-normal input voltages. This lockout circuitry in-
cludesapproximately 500 mV of hysteresisfor jitter-
free operation. Another feature of these PWM cir-
cuits is a latch following the comparator. Once a
PWM pulses has been terminated for any reason,
the outputs will remain off for the duration of the pe-
riod. The latch is reset with each clock pulse. The
output stages are totem-pole designs capable of
sourcing or sinking in excess of 200 mA. The
SG3525Aoutputstage features NOR logic, giving a
LOW output for an OFF state.
PIN CONNECTIONS AND ORDERING NUMBERS (top view)
Type
SG2525A
SG3525A
Plastic DIP
SG2525AN
SG3525AN
SO16
SG2525AP
SG3525AP
June 2000
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SG2525A-SG3525A
ABSOLUTE MAXIMUM RATINGS
Symbol
Vi
VC
IOSC
Io
IR
IT
Ptot
Tj
Tstg
Top
Parameter
Supply Voltage
Collector Supply Voltage
Oscillator Charging Current
Output Current, Source or Sink
Reference Output Current
Current through CT Terminal
Logic Inputs
Analog Inputs
Total Power Dissipation at Tamb = 70 °C
Junction Temperature Range
Storage Temperature Range
Operating Ambient Temperature : SG2525A
SG3525A
Value
40
40
5
500
50
5
– 0.3 to + 5.5
– 0.3 to Vi
1000
– 55 to 150
– 65 to 150
– 25 to 85
0 to 70
Unit
V
V
mA
mA
mA
mA
V
V
mW
°C
°C
°C
°C
THERMAL DATA
Symbol
Parameter
SO16 DIP16 Unit
Rth j-pins Thermal Resistance Junction-pins
Rth j-amb Thermal Resistance Junction-ambient
Rth j-alumina Thermal Resistance Junction-alumina (*)
Max
Max
Max
50
50 °C/W
80 °C/W
°C/W
* Thermalresistance junction-alumina with the device soldered on themiddle ofan alumina supporting substrate measuring 15 × 20 mm ; 0.65mm
thickness with infinite heatsink.
BLOCK DIAGRAM
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SG2525A-SG3525A
ELECTRICAL CHARACTERISTICS
(V# i = 20 V, and over operating temperature, unless otherwise specified)
Symbol
Parameter
REFERENCE SECTION
VREF Output Voltage
VREF Line Regulation
VREF Load Regulation
VREF/T* Temp. Stability
Test Conditions
SG2525A
SG3525A
Unit
Min. Typ. Max. Min. Typ. Max.
Tj = 25 °C
Vi = 8 to 35 V
IL = 0 to 20 mA
Over Operating Range
5.05 5.1 5.15
10 20
20 50
20 50
5
5.1 5.2
10 20
20 50
20 50
V
mV
mV
mV
* Total Output Variation Line, Load and
Temperature
5
5.2 4.95
5.25 V
Short Circuit Current
* Output Noise Voltage
VREF* Long Term Stability
OSCILLATOR SECTION * *
VREF = 0 Tj = 25 °C
10 Hz f 10 kHz,
Tj = 25 °C
Tj = 125 °C, 1000 hrs
80 100
40 200
20 50
80 100 mA
40 200 µVrms
20 50 mV
*,
*,
f/T*
Initial Accuracy
Voltage Stability
Temperature Stability
Tj = 25 °C
Vi = 8 to 35 V
Over Operating Range
±2
± 0.3
±3
±6
±1
±6
±2 ±6
±1 ±2
±3 ±6
%
%
%
fMIN Minimum Frequency RT = 200 KCT = 0.1 µF
120
120 Hz
fMAX Maximum Frequency RT = 2 KCT = 470 pF 400
400
KHz
Current Mirror
IRT = 2 mA
1.7 2 2.2 1.7 2 2.2 mA
*, Clock Amplitude
3 3.5
3 3.5
V
*, Clock Width
Tj = 25 °C
0.3 0.5 1 0.3 0.5 1
µs
Sync Threshold
1.2 2 2.8 1.2 2 2.8
V
Sync Input Current
Sync Voltage = 3.5 V
1 2.5
1 2.5 mA
ERROR AMPLIFIER SECTION (VCM = 5.1 V)
VOS Input Offset Voltage
0.5 5
2 10 mV
Ib Input Bias Current
Ios Input Offset Current
DC Open Loop Gain RL 10 M
1 10
1 10
11
60 75
60 75
µA
µA
dB
* Gain Bandwidth
Product
Gv = 0 dB Tj = 25 °C 1
2
12
MHz
*, „ DC Transconduct.
30 KRL 1 M
Tj = 25 °C
1.1 1.5
1.1 1.5
ms
Output Low Level
0.2 0.5
0.2 0.5
V
Output High Level
3.8 5.6
3.8 5.6
V
CMR Comm. Mode Reject. VCM = 1.5 to 5.2 V
60 75
60 75
dB
PSR
Supply Voltage
Rejection
Vi = 8 to 35 V
50 60
50 60
dB
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SG2525A-SG3525A
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Conditions
PWM COMPARATOR
Minimum Duty-cycle
Maximum Duty-cycle
Input Threshold
Zero Duty-cycle
Maximum Duty-cycle
* Input Bias Current
SHUTDOWN SECTION
Soft Start Current
VSD = 0 V, VSS = 0 V
Soft Start Low Level VSD = 2.5 V
Shutdown Threshold
To outputs, VSS = 5.1 V
Tj = 25 °C
Shutdown Input Current VSD = 2.5 V
* Shutdown Delay
VSD = 2.5 V Tj = 25 °C
OUTPUT DRIVERS (each output) (VC = 20 V)
Output Low Level
Isink = 20 mA
Output High Level
Isink = 100 mA
Isource = 20 mA
Under-Voltage Lockout
IC Collector Leakage
tr* Rise Time
tf* Fall Time
TOTAL STANDBY CURRENT
Isource = 100 mA
Vcomp and Vss = High
VC = 35 V
CL = 1 nF, Tj = 25 °C
CL = 1 nF, Tj = 25 °C
Is Supply Current
Vi = 35 V
SG2525A
Min. Typ. Max.
0
45 49
0.7 0.9
3.3 3.6
0.05 1
25 50 80
0.4 0.7
0.6 0.8 1
0.4 1
0.2 0.5
0.2 0.4
12
18 19
17 18
678
200
100 600
50 300
14 20
SG3525A
Min. Typ. Max.
0
45 49
0.7 0.9
3.3 3.6
0.05 1
25 50 80
0.4 0.7
0.6 0.8 1
0.4 1
0.2 0.5
0.2 0.4
12
18 19
17 18
678
200
100 600
50 300
14 20
Unit
%
%
V
V
µA
µA
V
V
mA
µs
V
V
V
V
V
µA
ns
ns
mA
* These parameters, although guaranteed over the recommended operating conditions, are not 100 % tested in production.
Tested at fosc = 40 KHz (RT = 3.6 K, CT = 10nF, RD = 0 ). Approximate oscillator frequency is defined by :
f= 1
CT (0.7 RT + 3 RD)
.DC transconductance (gM) relates to DC open-loop voltage gain (Gv) according to the following equation : Gv = gM RL whereRL is the resistance
from pin 9 to ground. The minimum gM specification is used to calculate minimum Gv when the error amplifier output is loaded.
4/12




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