RTL8180L Datasheet PDF - Realtek


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RTL8180L
Realtek

Part Number RTL8180L
Description WIRELESS LAN NETWORK INTERFACE CONTROLLER
Page 30 Pages

RTL8180L datasheet pdf
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RTL8180L
REALTEK WIRELESS LAN
NETWORK INTERFACE CONTROLLER
RTL8180
1. Features............................................................................ 2
2. General Description ........................................................ 3
3. Block Diagram................................................................. 4
4. Pin Assignments............................................................... 5
5. Pin Descriptions............................................................... 6
5.1 Power Management/Isolation Interface ...................... 6
5.2 PCI Interface .............................................................. 7
5.3 EEPROM Interface..................................................... 8
5.4 Power Pins.................................................................. 9
5.5 LED Interface ............................................................. 9
5.6 Attachment Unit Interface ........................................ 10
5.6.1 Intersil RF Chipset ............................................ 10
5.6.2 RFMD RF Chipset ........................................... 12
5.6.3 Philips RF Chipset ............................................ 13
5.7 Test, Clock and Other Pins....................................... 14
6. Register Descriptions .................................................... 15
6.1 TSFTR:TimingSynchronizationFunctionTimerRegister....... 17
6.2 BRSR: Basic Rate Set Register ................................ 17
6.3 BSSID: Basic Service Set ID ................................... 17
6.4 CR: Command Register............................................ 18
6.5 IMR: Interrupt Mask Register .................................. 19
6.6 ISR: Interrupt Status Register................................... 20
6.7 TCR: Transmit Configuration Register .................... 21
6.8 RCR: Receive Configuration Register...................... 22
6.9 9346CR: 93C46 (93C56) Command Register .......... 24
6.10 CONFIG 0: Configuration Register 0..................... 25
6.11 CONFIG 1: Configuration Register 1..................... 26
6.12 CONFIG 2: Configuration Register 2..................... 27
6.13 MSR: Media Status Register .................................. 27
6.14 CONFIG 3: Configuration Register 3..................... 28
6.15 CONFIG 4: Configuration Register 4..................... 29
6.16 PSR: Page Select Register ...................................... 30
6.17 SCR: Security Configuration Register.................... 30
6.18 BcnItv: Beacon Interval Register ........................... 31
6.19 AtimWnd: Atim Window Register ......................... 31
6.20 BintrItv: Beacon Interrupt Interval Register........... 31
6.21 AtimtrItv: Atim Interrupt Interval Register ............ 31
6.22 PhyDelay: Phy Delay Register ............................... 32
6.23 DK0: Default Key 0 Register ................................. 32
6.24 DK1: Default Key 1 Register ................................. 32
6.25 DK2: Default Key 2 Register ................................. 32
6.26 DK3: Default Key 3 Register ................................. 33
6.27 CONFIG 5: Configuration Register 5..................... 33
6.28 TPPoll: Transmit Priority Polling Register............. 34
6.29 CWR: Contention Window Register ...................... 35
6.30 RetryCTR: Retry Count Register............................ 35
6.31 RDSAR: Receive Descriptor Start Address Register .... 35
6.32 FER: Function Event Register ................................ 35
6.33 FEMR: Function Event Mask Register................... 36
6.34 FPSR: Function Present State Register................... 36
6.35 FFER: Function Force Event Register.................... 37
7. EEPROM (93C46 or 93C56) Contents........................ 38
7.1 Summary of RTL8180 EEPROM Registers ............. 40
7.2 Summary of EEPROM Power Management Registers ... 40
8. PCI Configuration Space Registers ............................. 41
8.1 PCI Bus Interface ..................................................... 41
8.1.1 Interrupt Control ............................................... 41
8.1.2 Latency Timer ................................................... 41
8.2 Bus Operation........................................................... 42
8.2.1 Target Read....................................................... 42
8.2.2 Target Write...................................................... 43
8.2.3 Master Read ...................................................... 44
8.2.4 Master Write ..................................................... 45
8.2.5 Configuration Access ........................................ 45
8.3 Packet Buffering ....................................................... 46
8.3.1 Transmit Buffer Manager.................................. 46
8.3.2 Receive Buffer Manager ................................... 46
8.3.3 Packet Recognition ........................................... 46
8.4 PCI Configuration Space Table ................................ 47
8.5 PCI Configuration Space Functions.......................... 49
8.6 Default Value After Power-on (RSTB Asserted)............ 53
8.7 PCI Power Management Functions........................... 54
8.8 VPD (Vital Product Data) ........................................ 55
9. Functional Description.................................................. 56
9.1 Transmit & Receive Operations ............................... 56
9.1.1 Transmit ............................................................ 56
9.1.2 Receive.............................................................. 61
9.2 Loopback Operation ................................................. 64
9.3 Tx Encapsulation ...................................................... 64
9.4 Rx Decapsulation...................................................... 64
9.5 Memory Functions.................................................... 65
9.5.1 Memory Read Line (MRL) ............................... 65
9.5.2 Memory Read Multiple (MRM)........................ 65
9.5.3 Memory Write and Invalidate (MWI) ............... 66
9.6 LED Functions.......................................................... 67
9.6.1 Link Monitor ..................................................... 67
9.6.2 Infrastructure Monitor....................................... 67
9.6.3 Rx LED ............................................................. 67
9.6.4 Tx LED ............................................................. 68
9.6.5 Tx/Rx LED........................................................ 68
9.6.6 LINK/ACT LED ............................................... 69
10. Application Diagram................................................... 70
11. Electrical Characteristics............................................ 71
11.1 Temperature Limit Ratings ..................................... 71
11.2 DC Characteristics.................................................. 71
11.3 AC Characteristics.................................................. 72
11.3.1 Serial EEPROM Interface Timing .................. 72
11.3.2 PCI Bus Operation Timing.............................. 73
11.3.3 Serial Interface Timing ................................... 81
11.3.4 RF Control Timing.......................................... 82
12. Mechanical Dimensions............................................... 84
2003/3/31
1
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1. Features
RTL8180L
l 128-Pin LQFP
l Supports descriptor-based buffer management
l Patented integrated Wireless LAN MAC and Direct
Sequence Spread Spectrum Baseband Processor in one chip
l Enhanced Signal Detector
l Processing Gain FCC compliance
l On-Chip A/D and D/A converters for I/Q Data, AGC, and
Adaptive Power Control
l Targeted for Multipath Delay Spreads 125ns at 11Mbps
l Supports Antenna Diversity
l 1 Mbps, 2 Mbps, 5.5 Mbps, and 11 Mbps operation
l PCI local bus network interface controller
² Compliant to PCI Revision 2.2
² Supports PCI clock 16.75MHz-40MHz
² Supports PCI target fast back-to-back transaction
² Supports Memory Read Line, Memory Read
Multiple, Memory Write and Invalidate
² Provides PCI bus master data transfers and PCI
memory space or I/O space mapped data transfers
of RTL8180's operational registers
² Supports PCI VPD (Vital Product Data)
² Supports ACPI, PCI power management
l Supports CardBus. The CIS can be stored in a 93C56.
l Supports 44MHz OSC as the internal clock source. The
frequency deviation of OSC must be within 25 PPM.
l Compliant to PC97, PC98, PC99 and PC2001 standards
l Supports Wake-On-LAN (WOL) function and remote
wake-up (Magic Packet* and Microsoft® wake-up frame)
l Supports 4 WOL signals (active high, active low,
positive pulse, and negative pulse)
l Supports auxiliary power-on internal reset, to be ready
for remote wake-up when main power remains off
l Supports auxiliary power auto-detect, and sets the
related capability of power management registers in PCI
configuration space
l Compliant to IEEE 802.11 and IEEE 802.11b standards
l Supports Short Preamble option
l Internal encryption/decryption engine executes IEEE
802.11 40 bits and 104 bits WEP
l Supports 11Mbps rates with automatic fallback to 5.5, 2,
and 1Mbps
l Includes a programmable, PCI burst size and early Rx
threshold
l Supports a 32-bit general-purpose timer with the
external PCI clock as clock source, to generate
timer-interrupt
l Contains two large independent transmit and receive
FIFO devices
l Advanced power saving mode when LAN function or
wakeup function is not used
l Uses 93C46 (64*16-bit EEPROM) or 93C56
(128*16-bit EEPROM) to store resource configuration,
ID parameter, and VPD data. The 93C56 can also be
used to store the CIS data structure for CardBus
applications.
l Supports LED pins for various network activity
indications
l Supports 1 general purpose input pin and up to 3 general
purpose output pins.
l Supports digital loopback capability on both ports
l Universal Chip for various Radio Front End for different
applications
l Supports software control on 3-wire bus on RF chipset.
l 3.3V and 1.8V power supplies needed
l 5V tolerant I/Os
l 0.18μ CMOS process
2003/3/31
2
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RTL8180L
2. General Description
The Realtek RTL8180 is a highly integrated and cost-effective wireless LAN network interface controller that integrates a
wireless LAN MAC and a direct sequence spread spectrum baseband processor into one chip. It provides 32-bit performance, PCI
bus master capability, and full compliance with IEEE 802.11 and IEEE 802.11b specifications.
The RTL8180 has on board A/D and D/A converters for analog I and Q inputs and outputs. Differential phase shift keying
modulation schemes DBPSK and DQPSK, with data scrambling capability, are available along with complementary code keying
to provide a variety of data rates. Both receive and transmit AGC functions obtain maximum performance in the analog portions
of the transceiver. The RTL8180 also includes a built-in enhanced signal detector to alleviate severe multipath effects. The target
environment for 11Mbps is 125ns RMS delay spread. It also supports short preamble and antenna diversity. For security issues,
the RTL8180 also implements a high performance internal WEP engine supporting up to 104 bit WEP.
It also supports Advanced Configuration Power management Interface (ACPI), PCI power management system for modern
operating systems that are capable of Operating System directed Power Management (OSPM) to achieve the most efficient power
management possible.
In addition to the ACPI feature, the RTL8180 also supports remote wake-up (including AMD Magic Packet and Microsoft®
wake-up frame) in both ACPI and APM environments. The RTL8180 is capable of performing an internal reset through the
application of auxiliary power. When the auxiliary power is applied and the main power remains off, the RTL8180 is ready and
waiting for the Magic Packet or wake-up frame to wake the system up. Also, the LWAKE pin provides four different output
signals including active high, active low, positive pulse, and negative pulse. The versatility of the RTL8180 LWAKE pin provides
motherboards with Wake-On-LAN (WOL) functionality.
PCI Vital Product Data (VPD) is also supported to provide the information that uniquely identifies hardware (i.e., the RTL8180
LAN card). The information may consist of part number, serial number, and other detailed information.
The RTL8180 supports an enhanced link list descriptor-based buffer management architecture, which is an essential part of a
design for a modern network interface card. It contributes to lowering CPU utilization. Also, the RTL8180 boosts its PCI
performance by supporting PCI Memory Read Line & Memory Read Multiple when transmitting, and Memory Write and
Invalidate when receiving.
The RTL8180 keeps network maintenance costs low and eliminates usage barriers. The RTL8180 is highly integrated and
requires no gluelogic or external memory.
2003/3/31
3
Rev1.2



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3. Block Diagram
MAC
PCI
Interface
EEPROM
Interface
LED Driver
Serial
Control
Power and TX/RX Timing Control Logic
Interrupt
Control
Logic
RTS, CTS,
ACK Frame
Generator
WEP
Engine
Checksum
Logic
FIFO
FIFO
Control
Logic
CCA/
NAV
Transmit/
Receive
Logic
Interface
RTL8180L
Radio and
Synthesizer
Control
From BBP
MAC/BBP
Interface
BBP, TX section
MAC/BBP
Interface
Scrambler
Coding
Digital
Filter
From MAC
Register
TX State
Machine
TX AGC
Control
BBP, RX section
MAC/BBP
Interface
Descrambler
Decoding
To MAC
Clear Channel
Assessment /
Signal Quality
RX AGC
Control
From MAC
Register
RX State
Machine
DAC
DAC
DAC
ADC
ADC
ADC
DAC
ADC
Antenna
Diversity
Control
TXI
TXQ
TXAGC
TXDET
RXI
RXQ
RXAGC
RSSI
ANTSEL+
ANTSEL-
2003/3/31
4
Rev1.2




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