PXA250 Datasheet PDF - Intel


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PXA250
Intel

Part Number PXA250
Description Application Processors
Page 30 Pages

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Intel® PXA250 and PXA210
Application Processors
Developer’s Manual
February 2002
Order Number: 278522-001



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Contents
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no
liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are
not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The PXA250 and PXA210 application processors may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled
platforms may require licenses from various entities, including Intel Corporation.
This document and the software described in it are furnished under license and may only be used or copied in accordance with the terms of the
license. The information in this document is furnished for informational use only, is subject to change without notice, and should not be construed as a
commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this
document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may
be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2002
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ii PXA250 and PXA210 Application Processors Developer’s Manual



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Contents
Contents
1 Introduction...................................................................................................................................1-1
1.1 Intel® XScale™ Core Features .........................................................................................1-1
1.2 System Integration Features..............................................................................................1-2
1.2.1 Memory Controller ................................................................................................1-2
1.2.2 Clocks and Power Controllers...............................................................................1-2
1.2.3 Universal Serial Bus (USB) Client.........................................................................1-3
1.2.4 DMA Controller (DMAC) .......................................................................................1-3
1.2.5 LCD Controller ......................................................................................................1-3
1.2.6 AC97 Controller ....................................................................................................1-3
1.2.7 Inter-IC Sound (I2S) Controller .............................................................................1-3
1.2.8 Multimedia Card (MMC) Controller .......................................................................1-3
1.2.9 Fast Infrared (FIR) Communication Port...............................................................1-4
1.2.10 Synchronous Serial Protocol Controller (SSPC)...................................................1-4
1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit....................................................1-4
1.2.12 GPIO .....................................................................................................................1-4
1.2.13 UARTs ..................................................................................................................1-4
1.2.14 Real-Time Clock (RTC).........................................................................................1-5
1.2.15 OS Timers.............................................................................................................1-5
1.2.16 Pulse-Width Modulator (PWM) .............................................................................1-5
1.2.17 Interrupt Control ....................................................................................................1-5
2 System Architecture .....................................................................................................................2-1
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
Overview ............................................................................................................................2-1
Package Types ..................................................................................................................2-2
Intel® XScale™ Microarchitecture Implementation Options..............................................2-2
2.3.1 Coprocessor 7 Register 4 - PSFS Bit ...................................................................2-3
2.3.2 Coprocessor 14 Registers 0-3 - Performance Monitoring.....................................2-3
2.3.3 Coprocessor 14 Register 6 and 7- Clock and Power Management......................2-3
2.3.4 Coprocessor 15 Register 0 - ID Register Definition ..............................................2-4
2.3.5 Coprocessor 15 Register 1 - P-Bit ........................................................................2-6
I/O Ordering .......................................................................................................................2-6
Semaphores ......................................................................................................................2-6
Interrupts............................................................................................................................2-7
Reset .................................................................................................................................2-7
Internal Registers...............................................................................................................2-8
Selecting Peripherals vs. General Purpose I/O .................................................................2-9
Power on Reset and Boot Operation .................................................................................2-9
Power Management...........................................................................................................2-9
Pin List .............................................................................................................................2-10
Processor Options ...........................................................................................................2-26
Memory Map ....................................................................................................................2-27
Register Address Summary .............................................................................................2-30
3 Clocks and Power Manager .........................................................................................................3-1
3.1 Clock Manager Introduction...............................................................................................3-1
3.2 Power Manager Introduction..............................................................................................3-2
iii PXA250 and PXA210 Application Processors Developer’s Manual



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Contents
3.3 Clock Manager...................................................................................................................3-2
3.3.1 32.768 kHz Oscillator............................................................................................3-4
3.3.2 3.6864 MHz Oscillator ..........................................................................................3-4
3.3.3 Core Phase Locked Loop .....................................................................................3-4
3.3.4 95.85 MHz Peripheral Phase Locked Loop ..........................................................3-5
3.3.5 147.46 MHz Peripheral Phase Locked Loop ........................................................3-6
3.3.6 Clock Gating .........................................................................................................3-6
3.4 Resets and Power Modes..................................................................................................3-6
3.4.1 Hardware Reset....................................................................................................3-7
3.4.2 Watchdog Reset ...................................................................................................3-7
3.4.3 GPIO Reset ..........................................................................................................3-8
3.4.4 Run Mode .............................................................................................................3-9
3.4.5 Turbo Mode ..........................................................................................................3-9
3.4.6 Idle Mode ............................................................................................................3-10
3.4.7 Frequency Change Sequence ............................................................................3-12
3.4.8 Sleep Mode.........................................................................................................3-14
3.4.9 Power Mode Summary .......................................................................................3-18
3.5 Power Manager Registers ...............................................................................................3-20
3.5.1 Power Manager Control Register .......................................................................3-21
3.5.2 Power Manager General Configuration Register................................................3-22
3.5.3 Power Manager Wake-Up Enable Register........................................................3-23
3.5.4 Power Manager Rising-Edge Detect Enable Register........................................3-24
3.5.5 Power Manager Falling-Edge Detect Enable Register .......................................3-25
3.5.6 Power Manager GPIO Edge Detect Status Register ..........................................3-26
3.5.7 Power Manager Sleep Status Register...............................................................3-27
3.5.8 Power Manager Scratch Pad Register ...............................................................3-28
3.5.9 Power Manager GPIO Sleep State Registers.....................................................3-29
3.5.10 Reset Controller Status Register ........................................................................3-30
3.5.11 Power Manager Register Locations....................................................................3-31
3.6 Clocks Manager Registers...............................................................................................3-32
3.6.1 Core Clock Configuration Register .....................................................................3-32
3.6.2 Clock Enable Register ........................................................................................3-34
3.6.3 Oscillator Configuration Register ........................................................................3-36
3.6.4 Clocks Manager Register Locations ...................................................................3-36
3.7 Coprocessor 14: Clock and Power Management ............................................................3-37
3.7.1 CCLKCFG Register (CP14 Register 6) ..............................................................3-37
3.7.2 PWRMODE Register (CP14 Register 7) ............................................................3-38
3.8 External Hardware Considerations ..................................................................................3-38
3.8.1 Power Supply Sequencing..................................................................................3-38
3.8.2 Power-On-Reset Considerations ........................................................................3-38
3.8.3 Power Supply Connectivity .................................................................................3-39
3.8.4 Driving the Crystal Pins from an External Clock Source.....................................3-39
3.8.5 Noise Coupling Between Driven Crystal Pins and a Crystal Oscillator...............3-39
4 System Integration Unit ................................................................................................................4-1
4.1 General-Purpose I/O..........................................................................................................4-1
4.1.1 GPIO Operation ....................................................................................................4-1
4.1.2 GPIO Alternate Functions.....................................................................................4-2
4.1.3 GPIO Register Definitions.....................................................................................4-6
4.1.4 GPIO Register Locations ....................................................................................4-21
iv PXA250 and PXA210 Application Processors Developer’s Manual




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