PDM41024 Datasheet PDF - Paradigm

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PDM41024
Paradigm

Part Number PDM41024
Description 1 Megabit Static RAM 128K x 8-Bit
Page 8 Pages


PDM41024 datasheet pdf
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Features
n High-speed access times
Com’l: 10, 12 and 15 ns
Ind’l: 12 and 15 ns
n Low power operation (typical)
- PDM41024SA
Active: 450 mW
Standby: 50 mW
- PDM41024LA
Active: 400 mW
Standby: 25mW
n Single +5V (±10%) power supply
n TTL-compatible inputs and outputs
n Packages
Plastic SOJ (300 mil) - TSO
Plastic SOJ (400 mil) - SO
Plastic TSOP (I)- T
PDM41024
Description
1 Megabit Static RAM
128K x 8-Bit
1
The PDM41024 is a high-performance CMOS static
RAM organized as 131,072 x 8 bits. Writing is
accomplished when the write enable (WE) and the
chip enable (CE1) inputs are both LOW and CE2 is
HIGH. Reading is accomplished when WE and CE2
remain HIGH and CE1 and OE are both LOW.
The PDM41024 operates from a single +5V power
supply and all the inputs and outputs are fully TTL-
compatible. The PDM41024 comes in two versions:
the standard power version (SA) and the low power
version (LA). The two versions are functionally the
same and differ only in their power consumption.
The PDM41024 is available in a 32-pin plastic TSOP
(I), and a 300-mil and 400-mil plastic SOJ.
2
3
4
5
6
Functional Block Diagram
Addresses
I/O 0
I/O 7
A0
A16
CE1
CE2
WE
OE
Control
Decoder
Input
Data
Control
Memory
Matrix
•••••
Column I/O
7
8
9
10
11
12
Rev. 3.3 - 4/09/98
1



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Pin Configuration
TSOP (I)
SOJ
PDM41024
A11 1
A9 2
A8 3
A13 4
WE 5
CE2 6
A15 7
Vcc 8
NC 9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
Pin Description
Name
A16-A0
I/O7-I/O0
OE
WE
CE1, CE2
NC
VCC
VSS
Description
Address Inputs
Data Inputs/Outputs
Output Enable Input
Write Enable Input
Chip Enable Inputs
No Connect
Power (+5V)
Ground
32 OE
31 A10
30 CE1
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 Vss
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
Vss 16
32 Vcc
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
Truth Table(1)
OE WE CE1 CE2 I/O
MODE
X X H X Hi-Z
Standby
X X X L Hi-Z
Standby
L H L H DOUT
Read
X L L H DIN
Write
H H L H Hi-Z Output Disable
NOTE: 1. H = VIH, L = VIL, X = DON’T CARE
Absolute Maximum Ratings (1)
Symbol Rating
VTERM
TBIAS
TSTG
PT
IOUT
Tj
Terminal Voltage with Respect to VSS
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Maximum Junction Temperature (2)
Com’l.
–0.5 to +7.0
–55 to +125
–55 to +125
1.0
50
125
Ind.
–0.5 to +7.0
–65 to +135
–65 to +150
1.0
50
145
Unit
V
°C
°C
W
mA
°C
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device.This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The cal-
culation should be of the form: Tj = Ta + P * θja where Ta is the ambient temperature, P
is average operating power and θja the thermal resistance of the package. For this
product, use the following θja values:
SOJ: 72o C/W
TSOP: 95o C/W
2 4/09/98 - Rev. 3.3



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PDM41024
Recommended DC Operating Condition
Symbol
Parameter
VCC
VSS
Industrial
Commercial
Supply Voltage
Supply Voltage
Ambient Temperature
Ambient Temperature
1Min.
Typ.
Max.
Unit
4.5 5.0 5.5
V
000V
2–40 25 85 °C
0 25 70 °C
DC Electrical Characteristics (VCC = 5.0V ± 10%)
Symbol
ILI
Parameter
Input Leakage Current
Test Conditions
VCC = MAX., VIN = VSS to VCC
ILO Output Leakage Current VCC = MAX.,
CE1 = VIH and CE2 = VIL,
VOUT = VSS to VCC
VIL Input Low Voltage
VIH Input High Voltage
VOL
Output Low Voltage
IOL = 8 mA, VCC = Min.
IOL = 10 mA, VCC = Min.
VOH
Output High Voltage
IOH = –4 mA, VCC = Min.
NOTE: 1. VIL(min) = –3.0V for pulse width less than 20 ns
Com’l/
Ind.
Com’l/
Ind.
PDM41024SA
Min.
–5
Max.
5
PDM41024LA
Min.
–1
Max.
1
–5 5 –1 1
–0.5(1) 0.8 –0.5(1) 0.8
2.2 6.0 2.2 6.0
— 0.4 — 0.4
— 0.5 — 0.5
2.4 — 2.4 —
Power Supply Characteristics
Symbol
ICC
ISB
ISB1
Parameter
Operating Current
CE1 = VIL and CE2 = VIH
f = fMAX = 1/tRC
VCC = Max.
IOUT = 0 mA
Standby Current
CE1 = VIH and CE2 = VIL
f = fMAX = 1/tRC
VCC = Max.
Full Standby Current
CE1 VHC and CE2 VLC
f=0
VCC = Max.
VIN VCC – 0.2V or 0.2V
Power
SA
-10 -12
Com’l. Com’l. Ind.
250 230 240
-15
Com’l. Ind.
185 195
LA 230 210 220 165 175
SA 80 70 70 55 55
LA 75 65 65 50 50
SA 20 20 25 10 15
LA 10 10 10 5 10
SHADED AREAS = PRELIMINARY DATA
NOTES: All values are maximum guaranteed values.
VLC 0.2V, VHC VCC – 0.2V
3
Unit
4µA
µA
5V
V
V
6V
V
7
8
9
10
11
12
Rev. 3.3 - 4/09/98
3



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PDM41024
Capacitance(1) (TA = +25°C, f = 1.0 MHz)
Symbol
Parameter
Max.
Unit
CIN Input Capacitance
8 pF
COUT
Output Capacitance
8 pF
NOTE:1. This parameter is determined by device characterization but is not production tested.
AC Test Conditions
Input pulse levels
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
VSS to 3.0V
3 ns
1.5V
1.5V
See Figures 1 and 2
DOUT
255
+5V
480
30 pF
Figure 1. Output Load Equivalent
DOUT
255
+5V
480
5 pF
Figure 2. Output Load Equivalent
(for tLZCE, tHZCE, tLZWE, tHZWE, tLZOE,
tHZOE)
Typical Delta tAA vs Capacitive Loading
5
4
3
2
1
0
0 30 60 90 120
Additional Lumped Capacitive Loading (pF)
Figure 3.
4 4/09/98 - Rev. 3.3



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