2.5 V and 3.3 V LVCMOS clock fan-out buffer
6. Functional description
The PCK9456 is a full static design supporting clock frequencies up to 250 MHz. The
signals are generated and re-timed on-chip to ensure minimal skew between the three
output banks (see Figure 1 “Functional diagram of PCK9456”).
Each of the three output banks can be individually supplied by 2.5 V or 3.3 V, supporting
mixed voltage applications. The FSELx pins choose between division of the input
reference frequency by one or two. The frequency divider can be set individually for each
of the three output banks. The PCK9456 can be reset and the outputs are disabled by
deasserting the MR/OE pin (logic HIGH state). Asserting MR/OE will enable the outputs.
All control inputs accept LVCMOS signals while the outputs provide LVCMOS compatible
levels with the capability to drive terminated 50 Ω transmission lines. The clock input is
low voltage PECL compatible for differential clock distribution support. Please consult the
PCK9446 speciﬁcation for a full CMOS compatible device. For series terminated
transmission lines, each of the PCK9456 outputs can drive one or two traces, giving the
devices an effective fan-out of 1 : 20. The device is packaged in a 7 mm × 7 mm LQFP32
Table 3 details the supported single and dual supply conﬁgurations.
Table 3. Supported single and dual supply conﬁgurations
Mixed voltage supply
3.3 V or 2.5 V 3.3 V
3.3 V or 2.5 V
 VCC is the positive power supply of the device core and input circuitry. VCC voltage deﬁnes the input
threshold and levels.
 VCC(bankA) is the positive power supply of the bank A outputs. VCC(bankA) voltage deﬁnes bank A output
 VCC(bankB) is the positive power supply of the bank B outputs. VCC(bankB) voltage deﬁnes the bank B output
levels. VCC(bankB) is internally connected to VCC.
 VCC(bankC) is the positive power supply of the bank C outputs. VCC(bankC) voltage deﬁnes bank C output
6.1 Function table
Function table (controls)
0 QA[0:2] frequency = fref
0 QB[0:2] frequency = fref
0 QC[0:3] frequency = fref
0 outputs enabled
QA[0:2] frequency = fref ÷ 2
QB[0:2] frequency = fref ÷ 2
QC[0:3] frequency = fref ÷ 2
internal reset; outputs disabled (3-state)
Product data sheet
Rev. 01 — 31 July 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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