PCK9456 Datasheet PDF - NXP

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PCK9456
NXP

Part Number PCK9456
Description 2.5 V and 3.3 V LVCMOS clock fan-out buffer
Page 18 Pages


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PCK9456
2.5 V and 3.3 V LVCMOS clock fan-out buffer
Rev. 01 — 31 July 2006
Product data sheet
1. General description
www.DataSheet4U.com
2. Features
The PCK9456 is a 2.5 V and 3.3 V compatible 1 : 10 clock distribution buffer designed for
low voltage mid-range to high-performance telecommunications, networking and
computing applications. Both 3.3 V, 2.5 V and dual supply voltages are supported for
mixed voltage applications. The PCK9456 offers 10 low-skew outputs and a differential
LVPECL clock input. The outputs are configurable and support 1 : 1 and 1 : 2 output to
input frequency ratios. The PCK9456 is specified for the extended temperature range of
40 °C to +85 °C.
I Configurable 10 outputs LVCMOS clock distribution buffer
I Compatible to single, dual and mixed 3.3 V/2.5 V voltage supply
I Wide range output clock frequency up to 250 MHz
I Designed for mid-range to high performance telecommunications, networking and
computer applications
I Supports high performance differential clocking applications
I Maximum output skew of 200 ps (150 ps within one bank)
I Selectable output configurations per output bank
I 3-stateable outputs
I Available in LQFP32 package
I Ambient operating temperature of 40 °C to +85 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Name Description
PCK9456BD
LQFP32 plastic low profile quad flat package; 32 leads;
body 7 × 7 × 1.4 mm
Version
SOT358-1



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Philips Semiconductors
4. Functional diagram
PCK9456
2.5 V and 3.3 V LVCMOS clock fan-out buffer
www.DataSheet4U.com
PCLK
PCLK
PCK9456
25 k
25 k
0.5VCC
CLK
CLK ÷ 2
FSELA
FSELB
FSELC
MR/OE
25 k
25 k
25 k
25 k
Fig 1. Functional diagram of PCK9456
bank A
0
1
bank B
0
1
bank C
0
1
QA0
QA1
QA2
QB0
QB1
QB2
QC0
QC1
QC2
QC3
002aab862
PCK9456_1
Product data sheet
Rev. 01 — 31 July 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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Philips Semiconductors
5. Pinning information
5.1 Pinning
PCK9456
2.5 V and 3.3 V LVCMOS clock fan-out buffer
www.DataSheet4U.com
n.c. 1
VCC 2
PECL_CLK 3
PECL_CLK 4
FSELA 5
FSELB 6
FSELC 7
GND 8
PCK9456BD
24 GND
23 QB0
22 VCCB
21 QB1
20 GND
19 QB2
18 VCCB
17 VCCC
002aab863
Fig 2. Pin configuration for LQFP32
5.2 Pin description
Table 2. Pin description
Symbol
Pin
PECL_CLK
3
PECL_CLK
4
FSELA
5
FSELB
6
FSELC
7
GND
8, 11, 15, 20,
24, 27, 31
VCCA
25, 29
VCCB
18, 22
Type
LVPECL
LVPECL
LVCMOS
LVCMOS
LVCMOS
supply
supply
supply
VCCC
9, 13, 17
supply
VCC
QA0, QA1, QA2
2
30, 28, 26
supply
LVCMOS
QB0, QB1, QB2
23, 21, 19
LVCMOS
QC0, QC1, QC2, QC3 10, 12, 14, 16 LVCMOS
MR/OE
32 LVCMOS
n.c. 1 -
Description
differential clock reference
low voltage positive ECL input
output bank divide select input
ground
positive voltage supply for output bank A
positive voltage supply for output bank B;
internally connected to VCC
positive voltage supply for output bank C
positive voltage supply core (VCC)
bank A outputs
bank B outputs
bank C outputs
internal reset and output 3-state control
not connected
PCK9456_1
Product data sheet
Rev. 01 — 31 July 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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Philips Semiconductors
PCK9456
2.5 V and 3.3 V LVCMOS clock fan-out buffer
6. Functional description
www.DataSheet4U.com
The PCK9456 is a full static design supporting clock frequencies up to 250 MHz. The
signals are generated and re-timed on-chip to ensure minimal skew between the three
output banks (see Figure 1 “Functional diagram of PCK9456”).
Each of the three output banks can be individually supplied by 2.5 V or 3.3 V, supporting
mixed voltage applications. The FSELx pins choose between division of the input
reference frequency by one or two. The frequency divider can be set individually for each
of the three output banks. The PCK9456 can be reset and the outputs are disabled by
deasserting the MR/OE pin (logic HIGH state). Asserting MR/OE will enable the outputs.
All control inputs accept LVCMOS signals while the outputs provide LVCMOS compatible
levels with the capability to drive terminated 50 transmission lines. The clock input is
low voltage PECL compatible for differential clock distribution support. Please consult the
PCK9446 specification for a full CMOS compatible device. For series terminated
transmission lines, each of the PCK9456 outputs can drive one or two traces, giving the
devices an effective fan-out of 1 : 20. The device is packaged in a 7 mm × 7 mm LQFP32
package.
Table 3 details the supported single and dual supply configurations.
Table 3. Supported single and dual supply configurations
Supply voltage
configuration
VCC[1]
VCC(bankA)[2]
VCC(bankB)[3]
3.3 V
3.3 V
3.3 V
3.3 V
Mixed voltage supply
3.3 V
3.3 V or 2.5 V 3.3 V
2.5 V
2.5 V
2.5 V
2.5 V
VCC(bankC)[4]
3.3 V
3.3 V or 2.5 V
2.5 V
GND
0V
0V
0V
[1] VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input
threshold and levels.
[2] VCC(bankA) is the positive power supply of the bank A outputs. VCC(bankA) voltage defines bank A output
levels.
[3] VCC(bankB) is the positive power supply of the bank B outputs. VCC(bankB) voltage defines the bank B output
levels. VCC(bankB) is internally connected to VCC.
[4] VCC(bankC) is the positive power supply of the bank C outputs. VCC(bankC) voltage defines bank C output
levels.
6.1 Function table
Table 4.
Control
FSELA
FSELB
FSELC
MR/OE
Function table (controls)
Default
0
0 QA[0:2] frequency = fref
0 QB[0:2] frequency = fref
0 QC[0:3] frequency = fref
0 outputs enabled
1
QA[0:2] frequency = fref ÷ 2
QB[0:2] frequency = fref ÷ 2
QC[0:3] frequency = fref ÷ 2
internal reset; outputs disabled (3-state)
PCK9456_1
Product data sheet
Rev. 01 — 31 July 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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NXP
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