PCA9575 Datasheet PDF - NXP Semiconductors


www.Datasheet-PDF.com

PCA9575
NXP Semiconductors

Part Number PCA9575
Description level translating - low voltage GPIO
Page 30 Pages

PCA9575 datasheet pdf
View PDF for PC
PCA9575 pdf
View PDF for Mobile


No Preview Available !

www.DataSheet4U.com
PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
with reset and interrupt
Rev. 03 — 9 November 2009
Product data sheet
1. General description
The PCA9575 is a CMOS device that provides 16 bits of General Purpose parallel
Input/Output (GPIO) expansion in low voltage processor and handheld battery powered
mobile applications and was developed to enhance the NXP family of I2C-bus I/O
expanders. The improvements include lower supply current, lower operating voltage of
1.1 V to 3.6 V, separate supply rails to allow voltage level translation anywhere between
1.1 V and 3.6 V, 400 kHz clock frequency, and smaller packaging. Any of the 16 I/O ports
can be configured as an input or output independent of each other and default on start-up
to inputs.
I/O expanders provide a simple solution when additional I/Os are needed while keeping
interconnections to a minimum; for example in battery powered mobile applications and
clamshell devices for interfacing to sensors, push buttons, keypad, etc. In addition to
providing a flexible set of GPIOs, it simplifies interconnection of a processor running at
one voltage level to I/O devices operating at a different (usually higher) voltage level.
PCA9575 has built-in level shifting feature that makes these devices extremely flexible in
mixed signal environments where communication between incompatible I/Os is required.
The core of PCA9575 can operate at a voltage as low as 1.1 V while each I/O bank can
operate in the range 1.1 V to 3.6 V. Bus hold with programmable on-chip pull-up or
pull-down feature for I/Os is also provided.
The output stage consists of two banks each of 8-bit configuration registers, input
registers, interrupt mask registers, output registers, bus-hold and pull-up/pull-down
registers and polarity inversion registers. These registers allow the system master to
program and configure 16 GPIOs through the I2C-bus.
The system master can enable the I/Os as either inputs or outputs by writing to the I/O
configuration register bits. The data for each input or output is kept in the corresponding
Input or Output register. The polarity of the read registers can be inverted with the Polarity
Inversion register (active HIGH or active LOW operation). Either a bus-hold function or
pull-up/pull-down feature can be selected by programming corresponding registers. The
bus-hold provides a valid logic level when the I/O bus is not actively driven. When
bus-hold feature is not selected, the I/O ports can be configured to have pull-up or
pull-down by programming the pull-up/pull-down configuration register.
An open-drain interrupt output pin (INT) allows monitoring of the input pins and is
asserted each time a change occurs on an input port unless that port is masked
(default = masked). A ‘GPIO All Call’ command allows programming multiple PCA9575s
at the same time even if they have different individual I2C-bus addresses. This allows
optimal code programming when more than one device needs to be programmed with the
same instruction or if all outputs need to be turned on or off at the same time. The internal



No Preview Available !

NXP Semiconductors
www.DataSheet4U.com
PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
Power-On Reset (POR) or hardware reset pin (RESET) initializes the two banks of 8 I/Os
as inputs, sets the registers to their default values and initializes the device state machine.
The I/O banks are held in its default state when the logic supply (VDD) is off.
The PCA9575 is available in 24-pin TSSOP, 28-pin TSSOP and HWQFN24 packages,
and is specified over the 40 °C to +85 °C industrial temperature range.
The 28-pin package provides four address select pins, allowing up to 16 PCA9575
devices to be connected with 16 different addresses on the same I2C-bus.
2. Features
I Separate supply rails for core logic and each of the two I/O banks provides voltage
level shifting
I 1.1 V to 3.6 V operation with level shifting feature
I Very low standby current: < 2 µA
I 16 configurable I/O pins organized as 2 banks that default to inputs at power-up
I Outputs:
N Totem pole: 1 mA source and 3 mA sink
N Independently programmable 100 kpull-up or pull-down for each I/O pin
N Open-drain active LOW interrupt (INT) output pin allows monitoring of logic level
change of pins programmed as inputs
I Inputs:
N Programmable bus hold provides valid logic level when inputs are not actively
driven
N Programmable Interrupt Mask Control for input pins that do not require an interrupt
when their states change or to prevent spurious interrupts default to mask at
power-up
N Polarity Inversion register allows inversion of the polarity of the I/O pins when read
I 400 kHz I2C-bus serial interface
I Compliant with I2C-bus Standard-mode (100 kHz)
I Active LOW reset (RESET) input pin resets device to power-up default state
I GPIO All Call address allows programming of more than one device at the same time
with the same parameters
I 16 programmable slave addresses using 4 address pins (28-pin TSSOP only)
I 40 °C to +85 °C operation
I ESD protection exceeds 6000 V HBM per JESD22-A114, 500 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I Packages offered: TSSOP28, TSSOP24, HWQFN24
PCA9575_3
Product data sheet
Rev. 03 — 9 November 2009
© NXP B.V. 2009. All rights reserved.
2 of 38



No Preview Available !

NXP Semiconductors
www.DataSheet4U.com
PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
3. Applications
I Cell phones
I Media players
I Multi-voltage environments
I Battery operated mobile gadgets
I Motherboards
I Servers
I RAID systems
I Industrial control
I Medical equipment
I PLCs
I Gaming machines
I Instrumentation and test measurement
4. Ordering information
Table 1. Ordering information
Type number Topside mark Package
Name
PCA9575PW2 PCA9575PW2 TSSOP28
PCA9575PW1 PA9575PW1 TSSOP24
PCA9575HF 575F
HWQFN24
Description
plastic thin shrink small outline package; 28 leads;
body width 4.4 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
plastic thermal enhanced very very thin quad flat package;
no leads; 24 terminals; body 4 × 4 × 0.75 mm
Version
SOT361-1
SOT355-1
SOT994-1
PCA9575_3
Product data sheet
Rev. 03 — 9 November 2009
© NXP B.V. 2009. All rights reserved.
3 of 38



No Preview Available !

NXP Semiconductors
5. Block diagram
www.DataSheet4U.com
PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
A0
A1
(1)
A2
A3
PCA9575
SCL
SDA
VDD
RESET
INPUT
FILTER
POWER-ON
RESET
8-bit
write pulse
read pulse
INPUT/
OUTPUT
PORTS
BANK 1
I2C-BUS/SMBus
CONTROL
8-bit
write pulse
read pulse
INPUT/
OUTPUT
PORTS
BANK 0
VDD(IO)1
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
VDD(IO)0
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
VDD
VSS
LP INT
FILTER
Remark: All I/Os are set to inputs at power-up and RESET.
(1) PCA9575PW2 only.
Fig 1. Block diagram of PCA9575
002aad562
PCA9575_3
Product data sheet
Rev. 03 — 9 November 2009
© NXP B.V. 2009. All rights reserved.
4 of 38




PCA9575 datasheet pdf
Download PDF
PCA9575 pdf
View PDF for Mobile


Similiar Datasheets : PCA9500 PCA9501 PCA9502 PCA9504A PCA9506 PCA9507 PCA9508 PCA9509 PCA9509 PCA9510 PCA9510A PCA9511 PCA9511A PCA9512 PCA9512A PCA9512B PCA9513 PCA9513A PCA9514 PCA9514A PCA9515 PCA9515A PCA9515A PCA9515B PCA9516 PCA9516A PCA9517 PCA9517 PCA9517 PCA9517A

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Privacy Policy + Contact