PCA9574 Datasheet PDF - NXP Semiconductors


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PCA9574
NXP Semiconductors

Part Number PCA9574
Description level translating - low voltage GPIO
Page 30 Pages

PCA9574 datasheet pdf
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PCA9574
8-bit I2C-bus and SMBus, level translating, low voltage GPIO
with reset and interrupt
Rev. 02 — 27 July 2009
Product data sheet
1. General description
The PCA9574 is a CMOS device that provides 8 bits of General Purpose parallel
Input/Output (GPIO) expansion in low voltage processor and handheld battery powered
mobile applications and was developed to enhance the NXP family of I2C-bus I/O
expanders. The improvements include lower supply current, lower operating voltage of
1.1 V to 3.6 V, dual and separate supply rails to allow voltage level translation anywhere
between 1.1 V and 3.6 V, 400 kHz clock frequency, and smaller packaging. Any of the
8 I/O ports can be configured as an input or output independent of each other and default
on start-up to inputs. I/O expanders provide a simple solution when additional I/Os are
needed while keeping interconnections to a minimum; for example in battery powered
mobile applications and clamshell devices for interfacing to sensors, push buttons,
keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of
a processor running at one voltage level to I/O devices operating at a different (usually
higher) voltage level. PCA9574 has built-in level shifting feature that makes these devices
extremely flexible in mixed signal environments where communication between
incompatible I/Os is required. The core of PCA9574 can operate at a voltage as low as
1.1 V while the I/O bank can operate in the range 1.1 V to 3.6 V. Bus hold with
programmable on-chip pull-up or pull-down feature for I/Os is also provided.
The system master can enable the I/Os as either inputs or outputs by writing to the I/O
configuration register bits. The data for each input or output is kept in the corresponding
Input or Output register. The polarity of the read register can be inverted with the Polarity
inversion register (active HIGH or active LOW operation). Either a bus-hold function or
pull-up/pull-down feature can be selected by programming corresponding registers. The
bus-hold provides a valid logic level when the I/O bus is not actively driven. When
bus-hold feature is not selected, the I/O ports can be configured to have pull-up or
pull-down by programming the pull-up/pull-down configuration register.
An open-drain interrupt output pin (INT) allows monitoring of the input pins and is
asserted each time a change occurs on an input port unless that port is masked
(default = masked). A ‘GPIO All Call’ command allows programming multiple PCA9574s
at the same time even if they have different individual I2C-bus addresses. This allows
optimal code programming when more than one device needs to be programmed with the
same instruction or if all outputs need to be turned on or off at the same time. The internal
Power-On Reset (POR) or hardware reset pin (RESET) initializes the 8 I/Os as inputs,
sets the registers to their default values and initializes the device state machine. The I/O
bank is held in its default state when the logic supply (VDD) is off.
One address select pin allows up to two PCA9574 devices to be connected with two
different addresses on the same I2C-bus.



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PCA9574
8-bit I2C-bus and SMBus, level translating, low voltage GPIO
The PCA9574 is available in TSSOP16, HVQFN16 and HXQFN16U packages and is
specified over the 40 °C to +85 °C industrial temperature range.
2. Features
I 400 kHz I2C-bus serial interface
I Compliant with I2C-bus Standard-mode (100 kHz)
I Separate supply rails for core logic and I/O bank provides voltage level shifting
I 1.1 V to 3.6 V operation with level shifting feature
I Very low standby current: < 1 µA
I 8 configurable I/O pins that default to inputs at power-up
I Outputs:
N Totem pole: 1 mA source and 3 mA sink
N Independently programmable 100 kpull-up or pull-down for each I/O pin
N Open-drain active LOW interrupt (INT) output pin allows monitoring of logic level
change of pins programmed as inputs
I Inputs:
N Programmable bus hold provides valid logic level when inputs are not actively
driven
N Programmable Interrupt Mask Control for input pins that do not require an interrupt
when their states change or to prevent spurious interrupts default to mask at
power-up
N Polarity inversion register allows inversion of the polarity of the I/O pins when read
I Active LOW reset (RESET) input pin resets device to power-up default state
I GPIO All Call address allows programming of more than one device at the same time
with the same parameters
I 2 programmable slave addresses using 1 address pin
I 40 °C to +85 °C operation
I ESD protection exceeds 7000 V HBM per JESD22-A114, 500 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I Packages offered: TSSOP16, HVQFN16 and HXQFN16U
3. Applications
I Cell phones
I Media players
I Multi voltage environments
I Battery operated mobile gadgets
I Motherboards
I Servers
I RAID systems
I Industrial control
I Medical equipment
I PLCs
PCA9574_2
Product data sheet
Rev. 02 — 27 July 2009
© NXP B.V. 2009. All rights reserved.
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PCA9574
8-bit I2C-bus and SMBus, level translating, low voltage GPIO
I Gaming machines
I Instrumentation and test measurement
4. Ordering information
Table 1. Ordering information
Type number Package
Name
Description
Version
PCA9574PW TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
PCA9574BS HVQFN16 plastic thermal enhanced very thin quad flat package; SOT758-1
no leads; 16 terminals; body 3 × 3 × 0.85 mm
PCA9574HR
HXQFN16U plastic thermal enhanced extremely thin quad flat
package; no leads; 16 terminals; UTLP based;
body 2 × 2 × 0.5 mm
SOT1046-1
4.1 Ordering options
Table 2. Ordering options
Type number Topside mark
PCA9574PW PCA9574
PCA9574BS
P74
PCA9574HR
74
Temperature range
Tamb = 40 °C to +85 °C
Tamb = 40 °C to +85 °C
Tamb = 40 °C to +85 °C
5. Block diagram
PCA9574
A0
SCL
SDA
INPUT
FILTER
VDD
RESET
POWER-ON
RESET
I2C-BUS/SMBus
CONTROL
8-bit
write pulse
read pulse
INPUT/
OUTPUT
PORTS
VDD(IO)
P0
P1
P2
P3
P4
P5
P6
P7
VDD
VSS
LP INT
FILTER
Remark: All I/Os are set to inputs at power-up and RESET.
Fig 1. Block diagram of PCA9574
002aad054
PCA9574_2
Product data sheet
Rev. 02 — 27 July 2009
© NXP B.V. 2009. All rights reserved.
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PCA9574
8-bit I2C-bus and SMBus, level translating, low voltage GPIO
data from
shift register
data from
shift register
write
configuration
pulse
write pulse
read pulse
configuration
register
DQ
FF
CK Q
DQ
FF
CK
output port
register
input port
register
DQ
FF
CK
VDD(IO)
BUS-HOLD
AND
PULL-UP/PULL-DOWN
CONTROL
100 k
Q1
Q2 ESD
protection
diode
INTERRUPT
MASK
output port
register data
VDD(IO)
P0 to P7
VSS
input port
register data
to INT
data from
shift register
write polarity
pulse
polarity
inversion
register
DQ
FF
CK
Fig 2. Simplified schematic of the I/Os (P0 to P7)
polarity
inversion
register data
002aad066
PCA9574_2
Product data sheet
Rev. 02 — 27 July 2009
© NXP B.V. 2009. All rights reserved.
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