PCA9541A Datasheet PDF - NXP Semiconductors


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PCA9541A
NXP Semiconductors

Part Number PCA9541A
Description 2-to-1 I2C-bus master selector
Page 30 Pages

PCA9541A datasheet pdf
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
Rev. 03 — 16 July 2009
Product data sheet
1. General description
The PCA9541A is a 2-to-1 I2C-bus master selector designed for high reliability dual
master I2C-bus applications where system operation is required, even when one master
fails or the controller card is removed for maintenance. The two masters (for example,
primary and back-up) are located on separate I2C-buses that connect to the same
downstream I2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master
and are used to select one master at a time. Either master at any time can gain control of
the slave devices if the other master is disabled or removed from the system. The failed
master is isolated from the system and will not affect communication between the on-line
master and the slave devices on the downstream I2C-bus.
Two versions are offered for different architectures. PCA9541A/01 with channel 0 selected
at start-up, and PCA9541A/03 with no channel selected after start-up.
The interrupt outputs are used to provide an indication of which master has control of the
bus. One interrupt input (INT_IN) collects downstream information and propagates it to
the 2 upstream I2C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let
the previous bus master know that it is not in control of the bus anymore and to indicate
the completion of the bus recovery/initialization sequence. Those interrupts can be
disabled and will not generate an interrupt if the masking option is set.
A bus recovery/initialization if enabled sends nine clock pulses, a not acknowledge, and a
STOP condition in order to set the downstream I2C-bus devices to an initialized state
before actually switching the channel to the selected master.
An interrupt is sent to the upstream channel when the recovery/initialization procedure is
completed.
An internal bus sensor senses the downstream I2C-bus traffic and generates an interrupt
if a channel switch occurs during a non-idle bus condition. This function is enabled when
the PCA9541A recovery/initialization is not used. The interrupt signal informs the master
that an external I2C-bus recovery/initialization needs to be performed. It can be disabled
and an interrupt will not be generated.
The pass gates of the switches are constructed such that the VDD pin can be used to limit
the maximum high voltage, which will be passed by the PCA9541A. This allows the use of
different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicate
with 5 V devices without any additional protection.
The PCA9541A does not isolate the capacitive loading on either side of the device, so the
designer must take into account all trace and device capacitances on both sides of the
device, and pull-up resistors must be used on all channels.
External pull-up resistors pull the bus to the desired voltage level for each channel. All I/O
pins are 6.0 V tolerant.



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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
An active LOW reset input allows the PCA9541A to be initialized. Pulling the RESET pin
LOW resets the I2C-bus state machine and configures the device to its default state as
does the internal Power-On Reset (POR) function.
2. Features
I 2-to-1 bidirectional master selector
I I2C-bus interface logic; compatible with SMBus standards
I PCA9541A/01 powers up with Channel 0 selected
I PCA9541A/03 powers up with no channel selected and either master can take control
of the bus
I Active LOW interrupt input
I 2 active LOW interrupt outputs
I Active LOW reset input
I 4 address pins allowing up to 16 devices on the I2C-bus
I Channel selection via I2C-bus
I Bus initialization/recovery function
I Bus traffic sensor
I Low Ron switches
I Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
I No glitch on power-up
I Supports hot insertion
I Software identical for both masters
I Low standby current
I Operating power supply voltage range of 2.3 V to 5.5 V
I 6.0 V tolerant inputs
I 0 Hz to 400 kHz clock frequency
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I Packages offered: SO16, TSSOP16, HVQFN16
3. Applications
I High reliability systems with dual masters
I Gatekeeper multiplexer on long single bus
I Bus initialization/recovery for slave devices without hardware reset
I Allows masters without arbitration logic to share resources
PCA9541A_3
Product data sheet
Rev. 03 — 16 July 2009
© NXP B.V. 2009. All rights reserved.
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
4. Ordering information
Table 1. Ordering information
Tamb = 40 °C to +85 °C
Type number
Package
Name
Description
Version
PCA9541AD/01 SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
PCA9541APW/01 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
PCA9541ABS/01 HVQFN16 plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; SOT629-1
body 4 × 4 × 0.85 mm
PCA9541AD/03 SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
PCA9541APW/03 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
PCA9541ABS/03 HVQFN16 plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; SOT629-1
body 4 × 4 × 0.85 mm
5. Marking
Table 2. Marking codes
Type number
Topside mark
PCA9541AD/01
PCA9541AD/1
PCA9541APW/01
9541A/1
PCA9541ABS/01
41A1
PCA9541AD/03
PCA9541AD/3
PCA9541APW/03
9541A/3
PCA9541ABS/03
41A3
PCA9541A_3
Product data sheet
Rev. 03 — 16 July 2009
© NXP B.V. 2009. All rights reserved.
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6. Block diagram
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
PCA9541A
SCL_MST0
SDA_MST0
A3
A2
A1
A0
RESET
VDD
SCL_MST1
SDA_MST1
INPUT
FILTER
STOP
DETECTION
POWER-ON
RESET
I2C-BUS
CONTROL
AND
REGISTER
BANK
INPUT
FILTER
STOP
DETECTION
BUS
SENSOR
SLAVE
CHANNEL
SWITCH
CONTROL
LOGIC
BUS
RECOVERY/
INITIALIZATION
OSCILLATOR
SCL_SLAVE
SDA_SLAVE
INT0
INT1
INTERRUPT
LOGIC
Fig 1. Block diagram of PCA9541A
INT_IN
VSS
002aae656
PCA9541A_3
Product data sheet
Rev. 03 — 16 July 2009
© NXP B.V. 2009. All rights reserved.
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