PCA9525 Datasheet PDF - NXP Semiconductors

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PCA9525
NXP Semiconductors

Part Number PCA9525
Description Simple 2-wire bus buffer
Page 22 Pages


PCA9525 datasheet pdf
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PCA9525
Simple 2-wire bus buffer
Rev. 1 — 25 February 2011
Product data sheet
1. General description
The PCA9525 is a monolithic CMOS integrated circuit for bus buffering in applications
including I2C-bus, SMBus, DDC, PMBus, and other systems based on similar principles.
The buffer extends the bus load limit by buffering both the SCL and SDA lines, allowing
the maximum permissible bus capacitance on both sides of the buffer.
The PCA9525 includes a unidirectional buffer for the clock signal, and a bidirectional
buffer for the data signal. Slave devices which employ clock stretching are therefore not
supported.
In its most basic implementation, the buffer will allow an extended number of slave
devices to be attached to one (or more) master devices. In this case, all master devices
would be positioned on the Sxx_IN side of the PCA9525.
The direction pin (DIR) further enhances this function by allowing the unidirectional clock
signal to be reversed, thus allowing master devices on both sides of the buffer.
The enable (EN) function allows sections of the bus to be isolated. Individual parts of the
system can be brought on-line successively. This means a controlled start-up using a
diverse range of components, operating speeds and loads is easily achieved.
2. Features and benefits
„ Simple impedance isolating buffer for 2-wire buses
„ 4 mA maximum static open-drain pull-down capability supports a wide range of bus
standards
„ Works with I2C-bus (Standard-mode, Fast-mode), SMBus (standard and high power
mode), and PMBus
„ Fast switching times allow operation in excess of 1 MHz
„ Enable allows bus segments to be disconnected
„ Hysteresis on inputs provides noise immunity
„ Operating voltages from 2.7 V to 5.5 V
„ Very low supply current
„ Uncomplicated characteristics suitable for quick implementation in most common
2-wire bus applications
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PCA9525
Simple 2-wire bus buffer
3. Applications
„ Electronic signs and displays
„ Game consoles/boxes
„ Gaming machine networks
„ TV/projector/monitor interconnection (DDC)
„ Power management systems
„ Desktop and portable computers
„ Security systems
4. Ordering information
Table 1. Ordering information
Type number Topside
mark
Package
Name
PCA9525D PCA9525 SO8
PCA9525DP 9525
TSSOP8
Description
plastic small outline package; 8 leads; body width 3.9 mm
plastic thin shrink small outline package; 8 leads; body width 3 mm
Version
SOT96-1
SOT505-1
5. Block diagram
enable
2.7 V to 5.5 V
R1 R2
EN 1
VDD
8
PCA9525
R3 R4
SDA
SDA_IN 6
7 SDA_OUT
SDA
SCL
direction
SCL_IN 3
DIR 5
Fig 1. Block diagram of PCA9525
4
VSS
2 SCL_OUT
SCL
002aaf329
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PCA9525
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
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6. Pinning information
6.1 Pinning
PCA9525
Simple 2-wire bus buffer
EN 1
SCL_OUT 2
SCL_IN 3
VSS 4
8 VDD
7 SDA_OUT
PCA9525D
6 SDA_IN
5 DIR
002aaf330
Fig 2. Pin configuration for SO8
EN 1
SCL_OUT 2
SCL_IN 3
VSS 4
PCA9525DP
8 VDD
7 SDA_OUT
6 SDA_IN
5 DIR
002aaf331
Fig 3. Pin configuration for TSSOP8
6.2 Pin description
Table 2. Pin description
Symbol
Pin
EN 1
SCL_OUT
2
SCL_IN
3
VSS 4
DIR 5
SDA_IN
6
SDA_OUT
7
VDD
8
Description
enable
clock buffer, slave side
clock buffer, master side
supply ground
clock direction
data buffer, master side
data buffer, slave side
positive supply
7. Functional description
Refer to Figure 1 “Block diagram of PCA9525”.
7.1 VDD, VSS — supply pins
The power supply voltage for the PCA9525 may be any voltage in the range 2.7 V to
5.5 V. The IC supply must be common with the supply for the bus. Hysteresis on the ports
is a percentage of the IC’s power supply, hence noise margin considerations should be
taken into account when selecting an operating voltage.
7.2 SCL_IN, SCL_OUT — clock signal inputs/outputs
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The clock signal buffer is unidirectional, although the direction may be reversed under
control of the direction pin (DIR). In normal bus operations, for example the I2C-bus, the
master device generates a unidirectional clock signal to the slave. For lowest cost, the
PCA9525 combines unidirectional buffering of the clock signal with a bidirectional buffer
for the data signal. Clock stretching is therefore not supported and slave devices that may
require clock stretching must be accommodated by the master adopting an appropriate
PCA9525
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
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PCA9525
Simple 2-wire bus buffer
clocking when communicating with them. The buffer includes hysteresis to ensure clean
switching signals are output, especially with slow rise times on high capacitively loaded
buses. Output ports are open-drain type and require external pull-up resistors.
7.3 SDA_IN, SDA_OUT — data signal inputs/outputs
The data signal buffer is bidirectional. The port (SDA_IN, SDA_OUT) which first falls
below the ‘lock voltage’ Vlock, will take control of the buffer direction and ‘lock out’ signals
coming from the opposite side. As the ‘input’ signal continues to fall, it will then drive the
‘output’ side LOW. Again, hysteresis is applied to the buffer to minimize the effects of
noise.
At some points during the communication, the data direction will reverse, e.g., when the
slave transmits an acknowledge (ACK), or responds with its register contents. During
these times, the controlling ‘input’ side will have to rise back above the unlock voltage
(Vunlock) before it releases the ‘lock’, which then allows the ‘output’ side to gain control,
and pull (what was) the ‘input’ side LOW again. This will cause a ‘pulse’ on the ‘input’ side,
which can be quite a long duration in high capacitance buses. However, this pulse will not
interfere with the actual data transmission, as it should not occur during times of clock line
transition (during normal I2C-bus and SMBus protocols), and thus data signal set-up time
requirements are still met. Ports are open-drain type and require external pull-up resistors.
7.4 Enable (EN) — activate buffer operations
The active HIGH enable input (EN) can be used to disable the buffer, for the purpose of
isolating sections of the bus. The IC should only be disabled when the bus is idle. This
prevents truncation of commands which may confuse other devices on the bus. Enable
(EN) may also be used to progressively activate sections of the bus during system
start-up. Bus sections slow to respond on power-up can be kept isolated from the main
system to avoid interference and collisions. The pin must be externally driven to a valid
state.
7.5 Direction (DIR) — clock buffer direction control
The direction input (DIR) is used to change the signal direction of the SCL ports. When the
DIR pin is logic LOW, the clock signal input is SCL_IN and the buffered output is
SCL_OUT. When the DIR pin is logic HIGH, the clock signal input is SCL_OUT and the
buffered output is SCL_IN. The pin must be externally driven to a valid state.
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PCA9525
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
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