PBL40309 Datasheet PDF - Ericsson

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PBL40309
Ericsson

Part Number PBL40309
Description 3.6 V Differential Power Amplifier for DECT Telecommunications system
Page 6 Pages


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Preliminary
PABuLgu4s0t 3200090
PBL 403 09
3.6 V Differential Power Amplifier
for DECT Telecommunications system
Description.
Key features.
The PBL 403 09 is a differential two stage silicon MMIC power amplifier intended for • 27 dBm output power
use in handheld cordless terminals in the 1900 MHz band. It can deliver more than 27
dBm at 1900 MHz into a balanced 50 load using a single 3.6 V supply. The circuit has • 25 dB small signal gain
a logic input to control transmit on/off and can be operated up to 100 % duty cycle with
minimum performance degradation. The circuit is housed in a specially designed • 50 % Power Added Efficiency
QSOP16 (150 mil body ) package and the implementation requires only few external
components.
• Simple logic on/off power control
25 GHz ft state-of-the-art deep trench isolated double-poly silicon bipolar process
with additional features for improved wireless performance has been used. On-chip • Battery charging conditions to 5.0 V
capacitors and inductors are used for the integrated internal matching network. Special
front-side metallized substrate contacts provide excellent ground paths from active • ESD protected
devices to the highly doped semiconductor substrate and package ground.
• Excellent ruggedness
• On-chip input and interstage
matching
• Differential input matched to 50
V CC
• Easy implementation with a simple
output matching network
RF In A
RF Out A & VCC
• Proven RF Silicon Technology
Reliability
• Low overall solution cost
Applications.
RF In B
RF Out B & VCC
• DECT
PoPwAe-rOCNontrol
Figure 1. Block diagram.
Figure 2. Package outlook.
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PBL 403 09
Maximum Ratings
Parameter
Supply voltage, continuous
All inputs (zener protection)
Operating case temperature
Storage temperature range
Symbol
Vcc
Top
TStg
Min.
-
-25
-30
Max.
5.2
6.5
+80
+100
Unit
V
V
°C
°C
Electrical Characteristics at room temperature
Unless otherwise stated the values below are valid for Vcc = 3.6 V, Pin = 4dBm, ZL = 50 and f = 1900 MHz, pulsed mode
t = 417 µs, duty cycle 1/24. All data as measured in the recommended typical application circuit.
Parameter
Frequency range
Power output
Power Added Efficiency
Power Added Efficiency
Small signal Gain
Isolation
2 nd and 3 rd harmonics
Input VSWR
Load Mismatch
Stability and spurious
Supply current
Supply current
Supply current
Rise time
Fall time
PA - ON = low
PA - ON = high
I ( PA - ON ) low
Condition
PA - ON = low
Pin = 10 dBm
Pin = 4 dBm
Pin = -10 dBm
PA - ON = high, Pin = 4 dBm
PA - ON = low, Pin < 4 dBm
Symbol
f
P
PAE
PAE
G
Pin = 4-10 dBm, Vcc = 5.2 V,
Load VSWR = 6:1 all phases
Pin = 4-10 dBm, Vcc = 3.0-5.2 V,
Load VSWR = 5:1 all phases
No input signal present,
IDC
PA - ON = low
Pin = 4 dBm
IDC
PA - ON = high
IDC
Pout to 1dB from final value.
tr
Measure time from switch to low.
Pout to less than -20 dB measured tf
from PA - ON pulse switched to high
Min.
Typ.
Max.
1880
1930
27 29
-
45 50
-
35 43
-
25.5 -
-35 -30
-35
1.6:1
3:1
no damage for 10 sec.
Unit
MHz
dBm
%
%
dB
dB
dBc
All spurious below - 36 dBm
135 mA
550
1 10
1
mA
µA
µA
2 µs
-0.5
Vcc -0.5
110
0.5
Vcc +0.5
130
V
V
µA
35
30
25
20
15
10
5
0
-10
-5
70
60
50
40
Pout [dBm]
Gain [dB]
PAE [%]
05
Pin [dBm]
10
30
20
10
0
15
Figure 3. Pout, Gain and PAE vs. Pin
Vcc = 3.6 V
2
32
30
28
26
24
2
Pin = 10 dBm
Pin = 4 dBm
2.5 3
Vcc [V]
3.5
4
Figure 4. Pout vs. Vcc for Pin = 4 dBm
and 10 dBm
54
52
50
48
46
44
42
40
2
Pin = 10 dBm
Pin = 4 dBm
2.5 3
Vcc [V]
3.5
4
Figure 5. PAE vs.Vcc for Pin = 4 dBm
and 10 dBm



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PBL 403 09
Figure 6. Pin configuration.
PA-ON 1
GND 2
RFinA 3
GND 4
GND 5
RFinB 6
GND 7
Vcc 8
Pin Descriptions:
Refer to pin configuration.
SO Name
Function
1 PA-ON
2 GND
3 RFinA
4 GND
5 GND
6 RFinB
7 GND
8 Vcc
PA On/Off Control pin (active low)
Common ground
RF input
Common ground
Common ground
RF input
Common ground
Supply voltage
16 GND
15 GND
14 RFoutA
13 GND
12 GND
11 RFoutB
10 GND
9 GND
SO Name
Function
9 GND
10 GND
11 RFoutB
12 GND
13 GND
14 RFoutA
15 GND
16 GND
Common ground
Common ground
RF output
Common ground
Common ground
RF output
Common ground
Common ground
Functional description.
PBL403 09 is a differential two stage integrated power amplifier intended for DECT. The circuit is manufactured in a bipolar 5.0 V
technology with additional features for improved wireless performance. Input and interstage matching is done completely on-chip,
tuned to 1.9 GHz, and only normal supply decoupling plus output matching is necessary. If the device is used in a single ended
environment, input and output transformers need to be added to the external circuitry.
PBL403 09 is optimized to work at a supply voltage of 3.6 V, but is able to operate between 2.7 and 5.2 V. At 3.6 V it can deliver up
to 31 dBm when driven into compression, while 27 dBm is guaranteed with an input power of 4 dBm. Best Power Added Efficiency
(PAE) is obtained close to maximum output power where PAE exeeds 50 %. Small signal gain is 25-26 dB. In a DECT handset with
the duty cycle 1/24, the average power dissipation in the circuit is low, normally between 30 to 40 mW. In the base station, the duty
cycle can increase and PBL403 09 can be operated at CW with a small penalty in power gain and output power (< 0.5 dB).
Operation is controlled through a power-on pin which is active low. When active, the current consumption is typically 135 mA without
any input signal present. When not active, current consumption is less than 10 µA.
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PBL 403 09
Application information.
DECT SINGLE ENDED POWER AMPLIFIER
When used as a single ended power amplifier, please refer to fig.7 and the test board fig. 8.
The 50 source impedance is converted to 50 differential with an LC-CL structure. Two series capacitors AC-couples the signal
to the input of PBL403 09. Suitable value of the capacitors is 1 to 5 pF in order to compensate for series inductance of the PCB and
package. Input impedance of the PBL403 09 is 50 differential.
The ideal collector load of the open collector RF output of PBL403 09 is about 11 per side. A matching and combination network to
50 single ended case is shown in fig. 7. A shunt capacitor (2.7 pF) transforms each output to 50 . Both 50 outputs are AC coupled
and then combined with an LC-CL structure to a 50 single ended output.
PA-ON
Vcc
10n
100p
100p
input
1.5p
3.9n 1.5p
1.5p 1.5p
3.9n
PBL 403 09
68 68
nn
33p
33p
2.7p 2.7p
GND
Figure 7. Evaluation setup including networks for unbalanced input/output.
1.1p
5.6n
1.1p
5.6n
output
Figure 8. Evaluation testboard.
4



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