P6408T2B5X2 Datasheet PDF - Apollo


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P6408T2B5X2
Apollo

Part Number P6408T2B5X2
Description Embedded MCP
Page 30 Pages

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eMCP Specification
Embedded MCP specification
P6408T2B5X2
Datasheet Preliminary Ver 1.0
Apollo Memory System Company
____________________________________________________________________________________________________________________
© 2014 Apollo memory system company
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eMCP Specification
<Product Specification>
-Compatible Approved Vendor List-
Chipset AVL
Chipset Model
eMCP PN
Mediatek
MT6582
08EMCP08-EL2BV100
Note 1: compatible AVL updated by 2014,Q4
-Device Summary-:
Product
Part number
Table 1 Device Summary
NAND
DRAM
CH & CS
For DRAM
P6408T2B5X2
8GB 8Gb 1CH, 2CS
-System Performance-
Operating
voltage
VCC=3.3V
VCCQ=1.8V/3.3V
VDD1 = 1.8V
VDD2, VDDQ = 1.2V
Table 2 e•MMCDevice Performance
Typical value
Read Sequential (MB/s)
Write Sequential (MB/s)
P6408T2B5X2
70
4
Note 1: Values given for an 8-bit bus width, running HS200 mode from proprietary tool, VCC=3.3V, VCCQ=1.8V.
Note 2: Performance numbers might be subject to changes without notice.
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eMCP Specification
< Embedded MMC- NAND>
Packaged NAND flash memory with e•MMC5.0 interface
Compliant with e•MMCSpecification Ver.4.4, 4.41,4.5&5.0
Supports three different data bus widths : 1 bit(default), 4 bits, 8 bits
- Data transfer rate: up to 52Mbyte/s (using 8 parallel data lines at 52 MHz)
- Single data rate : up to 200Mbyte/s @ HS200(Host clock @ 200MHz)
- Dual data rate : up to 104Mbyte/s @ 52MHz
Enhanced Write Protection with Permanent and Partial protection options
Supports Multiple User Data Partition with Enhanced User Data Area options
Supports Background Operations & High Priority Interrupt (HPI)
Error free memory access
- Internal error correction code (ECC) to protect data communication
- Internal enhanced data management algorithm
- Solid protection of sudden power failure safe-update operations for data content
Security
- Support secure bad block erase commands
- Enhanced write Protection with permanent and partial protection options
Supports Field Firmware Update(FFU)
Enhanced Device Life time
Optimal Size
Supports Production State Awareness
Supports Power Off Notification for Sleep
<Low power DDR2>
Density: 4Gbits
Organization
- × 32 bits: 16M words × 32 bits × 8 banks
- Row Address: R0 ~ R13
- Column Address: C0 ~ C9
Power supply
- VDD1 = 1.70V to 1.95V ,VDD2, VDDQ = 1.14V to 1.30V
Data rate: 1066Mbps max. (RL = 8)
Interface: HSUL_12
Burst lengths (BL): 4, 8, 16
Burst type (BT)
- Sequential (4, 8, 16)
- Interleave (4, 8)
Read latency (RL): 5, 6, 7, 8
Refresh cycles: 8192 cycles/28ms
Average refresh period: 3.4μs
- Storage temperature range: 40°C to +110°C
Operating junction temperature range TJ = -15°C to +80°C
____________________________________________________________________________________________________________________
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eMCP Specification
1. e•MMC™ Device and System
1.1. e•MMC™ System Overview
The e•MMCspecification covers the behavior of the interface and the Device controller. As part of this
specification the existence of a host controller and a memory storage array are implied but the operation
of these pieces is not fully specified.
The Apollo NAND Device contains a single chip MMC controller and NAND flash memory module. The
micro-controller interfaces with a host system allowing data to be written to and read from the NAND
flash memory module. The controller allows the host to be independent from details of erasing and
programming the flash memory.
Figure 1 e•MMCSystem Overview
____________________________________________________________________________________________________________________
© 2014 Apollo memory system company
4
CONFIDENTIAL




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