P1P8160A Datasheet PDF - ON Semiconductor

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P1P8160A
ON Semiconductor

Part Number P1P8160A
Description Low Jitter Clock Generator and Peak EMI Reduction IC
Page 6 Pages


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P1P8160A
Low Jitter Clock Generator
and Peak EMI Reduction IC
Product Description
P1P8160A is a versatile low jitter clock generator and spread
spectrum frequency modulator designed to reduce electromagnetic
interference (EMI) at the clock source, allowing system wide
reduction of EMI of down stream clock and data dependent signals.
The device allows significant system cost savings by reducing the
number of circuit board layers ferrite beads, shielding and other
passive components that are traditionally required to pass EMI
regulations.
P1P8160A modulates the output of a PLL in order to “spread” the
bandwidth of a synthesized clock, and more importantly, decreases the
peak amplitudes of its harmonics. This results in significantly lower
system EMI compared to the typical narrow band signal produced by
oscillators and most frequency generators. Lowering EMI by
increasing a signal’s bandwidth is called ‘spread spectrum clock
generation’.
P1P8160A accepts an input from either a 27 MHz fundamental
Crystal or from an external reference clock and generates a 100 MHz
Spread Spectrum clock. The device also features a 27MHz reference
clock output. Two Trilevel logic pins, SS1% and SS2% enables
selecting one of the eight different frequency deviations along with
SSOFF. Refer to Frequency Deviation Selection table. P1P8160A
operates over a supply voltage range of 3.3 V ± 10%. P1P8160A is
available in a 10 Pin WDFN (3 mm x 3 mm) package, over
temperature range 10°C to +85°C.
Features
LVCMOS Peak EMI Reduction
Input clock Frequency:
27 MHz: External Crystal or Reference Clock
Output clock Frequencies:
100 MHz Spread Spectrum Clock
27 MHz Refout
Two Trilevel Logic Pins for Selecting Eight Different Frequency
Deviations Along with SSOFF
Modulation Rate at 100 MHz: 32 kHz
Low CycleCycle Jitter, LT Jitter
Supply voltage: 3.3 V ± 10%
Temperature Range: 10°C to +85°C
10 Pin WDFN, 3 mm x 3 mm Package
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
Application
P1P8160A is targeted for use in a broad range of notebook, desktop
and embedded digital applications.
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MARKING
DIAGRAM
1
WDFN10
CASE 511BK
1P
8160A
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
PIN CONFIGURATION
CLKIN/XIN 1
VSS 2
SS2% 3
VDD1 4
ModOUT 5
10 XOUT
9 RefOUT
8 VDD2
7 SS1%
6 VSS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2010
October, 2010 Rev. 2
1
Publication Order Number:
P1P8160A/D



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P1P8160A
VDD1
VDD2
SS1%
SS2%
CLKIN/XIN
XOUT
Crystal
Oscillator
PLL
ModOUT
RefOUT
2
VSS
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
Pin#
Pin Name
1 CLKIN / XIN
2 VSS
3 SS2%
4 VDD1
5 ModOUT
6 VSS
7 SS1%
8 VDD2
9 RefOUT
10 XOUT
Type
I
P
I
O
P
I
P
O
O
Description
Crystal connection or External Reference Clock Input.
Ground to entire chip
Frequency Deviation Selection. Trilevel logic pin. Has an internal pull down resistor.
Refer to Frequency Deviation Selection table
Supply Voltage for 100 MHz ModOUT
Buffered 100MHz spread spectrum clock output
Ground to entire chip
Frequency Deviation Selection. Trilevel logic pin. Has an internal pull down resistor.
Refer to Frequency Deviation Selection table
Supply Voltage for 27 MHz RefOUT
Buffered reference clock output
Crystal connection. If using an external reference, this pin must be left unconnected.
3 Level Digital Logic
SS1% and SS2% digital inputs are designed to sense 3
different logic levels designated as High “1”, Low “0” and
Middle “M”. With this 3Level digital inputs, 9 different
logic states can be detected.
Use 5k/5k resistor divider at SS1% and SS2% pins from
VDD to VSS to obtain VDD/2, Middle “M” logic level as
shown:
Logic
Control Pins
1 SS1%, SS2% to VDD
M SS1%, SS2%
0
SS1%, SS2% to VSS
(UNCONNECTED)
VDD
VDD
5k
5k
VSS
VSS
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Table 2. FREQUENCY DEVIATION SELECTION TABLE
SS2% (Pin#3)
SS1% (Pin#7)
LL
LM
LH
ML
MM
MH
HL
HM
HH
Deviation at 100 MHz (%) (Pin#5)
SSOFF
0.5
2.5
0.25
0.75
1
1.5
2
3
ModRate (kHz)
32
Table 3. OPERATING CONDITIONS
Symbol
Parameter
VDD Voltage on any pin with respect to VSS
TA Operating Temperature
CL Load Capacitance
CIN Input Capacitance
Min Max Unit
2.97 3.63 V
10 +85 °C
15 pF
7 pF
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Rating
Unit
VDD, VIN
Voltage on any pin with respect to Ground
0.5 to +4.6
V
TSTG
Storage Temperature
65 to +125
°C
Ts Max. Soldering Temperature (10 sec)
260 °C
TJ Junction Temperature
150 °C
TDV Static Discharge Voltage (As per JEDEC STD 22A114B)
2 kV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may
affect device reliability.
Table 5. DC ELECTRICAL CHARACTERISTICS
(VDD = 3.3 V ± 10%, Ambient Temperature Range: 10°C to +85°C unless otherwise specified)
Symbol
Parameter
Min Typ Max Unit
VDD Supply Voltage
2.97 3.3 3.63 V
VIL Input Low Voltage (CLKIN/XIN, SS1%, SS2% Inputs)
0
0.2 V
VIM Input Middle Voltage (SS1%, SS2% Inputs)
0.4 x VDD
0.6 x VDD
V
VIH Input High Voltage (CLKIN/XIN, SS1%, SS2% Inputs)
0.9 x VDD
VDD
V
VOL Output Low Voltage (ModOUT, RefOUT)
IOL = 15 mA
0.4 V
VOH Output High Voltage (ModOUT, RefOUT)
IOH = 15 mA
2.4
V
IDD Dynamic Supply Current (CL = 15 pF, VDD = 3.63 V, T = +85°C)
22 mA
CIN1
Input Capacitance (XIN and XOUT)
6.0 pF
CIN2
Input Capacitance (SS1%, SS2% Inputs)
7.0 pF
RPD Pull Down Resistor (SS1%, SS2% Inputs)
100 200 250 kW
NOTE: The voltage on any input or I/O pin cannot exceed the power pin during power up.
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P1P8160A
Table 6. AC ELECTRICAL CHARACTERISTICS
(VDD = 3.3 V ± 10%, Ambient Temperature Range: 10°C to +85°C unless otherwise specified)
Symbol
Parameter
fIN
fOUT
tLH, tHL
(Note 2)
tLH, tHL
(Note 2)
TDCOUT
(Notes 1, 2)
Input Clock frequency (Tolerance: ±10ppm)
ModOUT Clock frequency (SS1% & SS2% = 0) (Tolerance: ±30ppm)
RefOUT Clock frequency (Tolerance: ±30ppm)
RefOUT Rise and Fall time
(Measured between 20% to 80%)
CL = 5 pF
CL = 15 pF
ModOUT Rise and Fall time
(Measured between 20% to 80%)
CL = 5 pF
CL = 15 pF
Output Clock Duty Cycle
TJC
(Notes 1, 2)
CycleCycle Jitter (For ModOUT, RefOUT)
(NotTesJL1, 2)
Long Term Jitter (10k cycles)
27 MHz, RefOUT
100 MHz ModOUT (SSOFF)
(NotteOsN1, 2)
Power Up Time
(Stable power supply, valid input clock to valid Clock on ModOUT).
tSS%
(Notes 1, 2)
Spread Percentage Setting Time
(Time from SS1%/SS2% change to stable ModOUT with change in spread %)
MF
(Notes 1, 2)
Modulation Frequency
FMTSR
(Notes 1, 2)
Frequency Modulation Type and Slew Rate (Triangular Modulation Profile)
1. Parameters are specified with 15 pF loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production
Min
45
31
Typ Max Unit
27 MHz
100 MHz
27
0.75 1.5
ns
1.25 2.0
0.75 1.0
ns
1.25 1.75
50 55 %
125 200
ps
150 300
350 600
5 ms
1 ms
32 33 kHz
0.125 %/ms
R
Crystal
Rx
CL CL
Figure 2. Typical Crystal Interface Circuit
CL = 2 * (CP – CS),
Where CP = Load capacitance of crystal specified in a Crystal Datasheet
CS = Stray capacitance due to CIN, PCB, Trace etc.
CL = Load capacitance to be used
Rx is used to reduce power dissipation in the Crystal
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