NJU26103 Datasheet PDF - JRC

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NJU26103
JRC

Part Number NJU26103
Description Delay
Page 8 Pages


NJU26103 datasheet pdf
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NJU26103
Digital Signal Processor for TV
General Description
The NJU26103 is a high performance 24-bit digital audio processor for TV that
has a QFP32-pin small package.
The NJU26103 provides an internal delay memory to adjust the output delay
time for lip sync. Moreover, the NJU26103 adopts SRS WOW technology..
Package
FEATURES
NJU26103FR1
- Software
3D sound : SRS WOW audio technology
Variable 2 Channels Audio Delay (16 bit data width).
fs=48kHz : Max. 42ms, fs=44.1kHz : Max. 46ms, fs=32kHz : Max. 64ms
- Hardware
24bit Fixed-point Digital Signal Processing
Maximum System Clock Frequency : 38MHz Max.
Digital Audio Interface
Digital Audio Format
: 2 Input ports / 1 Output ports
: I2S 24bit, Left- justified, Right-justified, BCK : 32/64fs
Master / Slave Mode
: Master Mode MCK 1/2 fclk, 1/3 fclk
ex. MCK = 384Fs(1/2) or MCK = 256Fs(1/3) at fclk=768Fs
Power Supply
: 2.5V
Input terminal
: 3.3V Input tolerant
Package
: QFP32-R1 (Pb-Free)
Two kinds of micro computer interface : I2C bus (standard-mode/100kbps)
: Serial interface (4 lines: clock, enable, input data, output data)
The detail hardware specification is described in the “ NJU26100 Series Hardware Data Sheet”.
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Function Block Diagram
AD1/SDIN AD2/SSb
NJU26103
SCL/SCK
SDA/SDOUT
RESETb
MCK
XI
XO
SERIAL
HOST
INTERFACE
DSP ARITHMETIC UNIT
PROGRAM
CONTROL
ALU
24-BIT x 24-BIT
MULTIPLIER
TIMING
GENERATOR
ADDRESS GENERATION UNIT
SERIAL AUDIO
INTERFACE
L/R
DELAY
RAM
DATA
RAM
FIRMWARE
ROM
GPIO AND
CONFIGURATION
INTERFACE
DSP Block Diagram
Fig. 1 NJU26103 Block Diagram
SDI0
Lin
Rin
Lin
Rin
SDI1
Delay
WOW
SDO0
Lout
Rout
Fig. 2 NJU26103 Function Diagram
BCKO
LRO
SDO0
SDI0
SDI1
BCKI
LRI
SEL1
-2-
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Pin Configuration
SDI0
SDI1
TEST
LRI
BCKI
MCK
BCKO
LRO
NJU26103
NJU26103
16 TEST
15 VSSC
14 VDDC
13 RESETb
12 VSSO
11 XO
10 XI
9 VDDO
Pin Description
Fig. 3 NJU26103Pin Configuration
Table 1 Pin Description
No. Symbol I/O
Description
1
2
TEST
O Open
3 SDO0
O Audio Data Output 0 L/R
4 SEL1 *1 I Select I2C or Serial bus
5 SCL/SCK
I I2C Clock / Serial Clock
6
SDA/SDOUT
I/O
I2C I/O / Serial Output
This pin requires a pull-up resistance.
7 AD1/SDIN
I I2C Address / Serial Input
8 AD2/SSb
I I2C Address / Serial Enable
9 VDDO
-- OSC Power Supply +2.5V
10 XI
I X’tal Clock Input
11 XO
O OSC Output
12 VSSO
-- OSC GND
13 RESETb
I RESET (active Low)
14 VDDC
-- Core Power Supply +2.5V
15 VSSC
-- Core GND
16 TEST
*2
I/O Open
* I : Input,
O : Output,
I/O: Bi-directional
*1 SEL1 : Input
No. Symbol
17
18
VDDC
19
20
VSSC
21 VDDR
22
23
24
VSSR
25 SDI0
26 SDI1
27 TEST
28 LRI
29 BCKI
30 MCK
31 BCKO
32 LRO
I/O Description
-- Core Power Supply +2.5V
-- Core GND
-- I/O Power Supply +2.5V
-- I/O GND
I Audio Data Input 0 L/R
I Audio Data Input 1 L/R
I Connect to GND
I LR Clock Input
I Bit Clock Input
O Master Clock Output
O Bit Clock Output
O LR Clock Output
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*2 TEST : Bi-directional
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