NJU26102 Datasheet PDF - JRC

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NJU26102
JRC

Part Number NJU26102
Description Eala / BBE ViVA / ViVA+ / ViVA2 / Mach3Bass / QFP32-R1
Page 8 Pages


NJU26102 datasheet pdf
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NJU26102
Digital Signal Processor for TV
General Description
Package
The NJU26102 is a digital signal processor that provides Delay, eala, ViVA2+,
PEQ, and AGC.
The NJU26102 is suitable for audio products such as TV, CD radio- cassette,
speakers system, and others.
FEATURES
NJU26102FR1
- Software
3D sound : eala (NJRC Original Surround),
BBE ViVA, BBE ViVA+
Sound Enhancement: : BBE, BBE Mach3Bass
AGC
5Band PEQ
Tone Control
Audio Delay ( fs=48kHz : Max. 25ms, fs=44.1kHz : Max. 27ms, fs=32kHz : Max. 37ms )
Master Volume
WatchDog Clock Output
- Hardware
24bit Fixed-point Digital Signal Processing
Maximum System Clock Frequency : 38MHz Max.
Digital Audio Interface
Digital Audio Format
: 3 Input ports / 3 Output ports
: I2S 24bit, Left- justified, Right-justified, BCK : 32/64fs
Master / Slave Mode
: Master Mode MCK 1/2 fclk, 1/3 fclk
ex. MCK = 384Fs(1/2) or MCK = 256Fs(1/3) at fclk=768Fs
Power Supply
: 2.5V
Input terminal
: 3.3V Input tolerant
Package
: QFP32-R1 (Pb-Free)
Two kinds of micro computer interface : I2C bus (standard-mode/100kbps)
: Serial interface (4 lines: clock, enable, input data, output data)
The detail hardware specification is described in the “ NJU26100 Series Hardware Data Sheet”.
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Function Block Diagram
AD1/SDIN AD2/SSb
NJU26102
SCL/SCK
SDA/SDOUT
RESETb
MCK
XI
XO
SERIAL
HOST
INTERFACE
DSP ARITHMETIC UNIT
PROGRAM
CONTROL
ALU
24-BIT x 24-BIT
MULTIPLIER
TIMING
GENERATOR
ADDRESS GENERATION UNIT
SERIAL AUDIO
INTERFACE
L/R
DELAY
RAM
DATA
RAM
FIRMWARE
ROM
GPIO AND
CONFIGURATION
INTERFACE
BCKO
LRO
SDO0~
SDO2
SDI0~
SDI2
BCKI
LRI
SEL1
DSP Block Diagram
Fig. 1 NJU26102 Block Diagram
SDI0
SDI1
SW2
SW1
Delay
3D
Enhancement
SDO1
SDO0
EQ
Trim
SW3
SW4
SW5
eala(stereo)
BBE
SW6
AGC
SW7
5Band
PEQ
SDI2
AGC
*2
Simulated Stereo
BBE Mach3 Bass
*1
HPF +
4PEQ
BBE ViVA (3D, BBE)
T.C. +
BBE ViVA+ (3D, BBE, Mach3Bass)
3PEQ
SW8
BBE ViVA2+ (3D, BBE, Mach3Bass, AGC)
HPF+T.C.
+2PEQ
Master Vol.
AGC
*3
SW10
SW9
Note 1. only one AGCs(*1, *2, *3) should be used.
Note 2. Do not use *1AGC and *3AGC during BBE ViVA2 being in
use.
Continuous
Siginal Det.
CLOCK GENERATOR
SDO2
WDC
Fig. 2 NJU26102 Function Diagram
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Pin Configuration
SDI0
SDI1
SDI2
LRI
BCKI
MCK
BCKO
LRO
NJU26102
NJU26102
16 WDC
15 VSSC
14 VDDC
13 RESETb
12 VSSO
11 XO
10 XI
9 VDDO
Pin Description
Fig. 3 NJU26102 Pin Configuration
Table 1 Pin Description
No. Symbol I/O
Description
1 SDO2
O Audio Data Output 2 L/R
2 SDO1
O Audio Data Output 1 L/R
3 SDO0
O Audio Data Output 0 L/R
4 SEL1 *1 I Select I2C or Serial bus
5 SCL/SCK
I I2C Clock / Serial Clock
6
SDA/SDOUT
I/O
I2C I/O / Serial Output
This pin requires a pull-up resistance.
7 AD1/SDIN
I I2C Address / Serial Input
8 AD2/SSb
I I2C Address / Serial Enable
9 VDDO
10 XI
11 XO
12 VSSO
-- OSC Power Supply +2.5V
I X’tal Clock Input
O OSC Output
-- OSC GND
13 RESETb
14 VDDC
I RESET (active Low)
-- Core Power Supply +2.5V
15 VSSC
-- Core GND
16 WDC *2 O Clock for Watch Dog Timer
* I : Input,
O : Output,
I/O: Bi-directional
*1 SEL1 : Input
*2 WDC : Output
No. Symbol
17
18
VDDC
19
20
VSSC
21 VDDR
22
23
24
VSSR
25 SDI0
26 SDI1
27 SDI2
28 LRI
29 BCKI
30 MCK
31 BCKO
32 LRO
I/O Description
-- Core Power Supply +2.5V
-- Core GND
-- I/O Power Supply +2.5V
-- I/O GND
I Audio Data Input 0 L/R
I Audio Data Input 1 L/R
I Audio Data Input 2 L/R
I LR Clock Input
I Bit Clock Input
O Master Clock Output
O Bit Clock Output
O LR Clock Output
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Digital Audio Interface
The NJU26102 audio interface provides industry standard serial data formats of I2S, MSB-first left-justified or
MSB-first right-justified. The NJU26102 audio interface provides three data inputs, SDI0, SDI1, SDI2 and three data
outputs, SDO0, SDO1, SDO2 as shown in table 2, table 3 and Fig.2. An audio interface input and output data format
become the same data format.
Table 2
Pin No.
25
26
27
Serial Audio Input Pin
Symbol
Description
SDI0 Audio Data Input 0
SDI1 Audio Data Input 1
SDI2 Audio Data Input 2
L/R
L/R
L/R
Table 3
Pin No.
3
2
1
Serial Audio Output Pin
Symbol
Description
SDO0 Audio Data Output 0
SDO1 Audio Data Output 1
SDO2 Audio Data Output 2
L/R
L/R
L/R
Host Interface
The NJU26102 can be controlled via Serial Host Interface (SHI) using either of two serial bus format : 4-Wire serial
bus or I2C bus.(Table 4) Data transfers are in 8 bit packets (1 byte) when using either format.
Serial Host Interface Pin Description.(Table 5)
Table 4 Serial Host Interface Pin Description
Pin No.
4
Symbol
SEL1
Setting
“Low”
“High”
Host Interface
I2C bus
4-Wire serial bus
Table 5 Serial Host Interface Pin Description
Pin No.
Symbol
(I2C bus / Serial)
I2C bus Format
4-Wire Serial bus Format
5 SCL / SCK
6 SDA / SDOUT
7 AD1 / SDIN
8 AD2 / SSb
Serial Clock
Serial Data Input/Output
(Open Drain Input/Output)
I2C bus address Bit1
I2C bus address Bit2
Serial Clock
Serial Data Output
(CMOS)
Serial Data Input
Serial enable
Note : SDA /SDOUT pin is a bi-directional open drain.
SDA /SDOUT output is normal CMOS output in case of 4-Wire Serial bus mode and SSb=”Low”.
SDA /SDOUT output is Hi-Z state in case of 4-Wire Serial bus mode and SSb=”High”. This pin
requires a pull-up resister in both 4-Wire serial and I2C bus mode.
-4-
Ver.2006-11-27



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