NB3M8302C Datasheet PDF - ON Semiconductor

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NB3M8302C
ON Semiconductor

Part Number NB3M8302C
Description 3.3V 200 MHz 1:2 LVCMOS/LVTTL Low Skew Fanout Buffer
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NB3M8302C datasheet pdf
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NB3M8302C
3.3 V 200 MHz 1:2
LVCMOS/LVTTL Low Skew
Fanout Buffer
Description
The NB3M8302C is 1:2 fanout buffer with LVCMOS/LVTTL input
and output. The device supports the core supply voltage of 3.3 V (VDD
pin) and output supply voltage of 2.5 V or 3.3 V (VDDO pin). The
VDDO pin powers the two single ended LVCMOS/LVTTL outputs.
The NB3M8302C is Form, Fit and Function (pin to pin) compatible
to ICS8302 and ICS8302I. The NB3M8302C is qualified for industrial
operating temperature range.
Features
Input Clock Frequency up to 200 MHz
Low Output to Output Skew: 25 ps typical
Low Part to Part Skew: 250 ps typical
Low Additive RMS Phase Jitter
Input Clock Accepts LVCMOS/ LVTTL Levels
Operating Voltage:
Core Supply: VDD = 3.3 V ±5%
Output Supply: VDDO = 3.3 V ±5% or 2.5 V ±5%
Operating Temperature Range:
Industrial: −40°C to +85°C
These Devices are Pb−Free and are RoHS Compliant
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8
1
SOIC−8
D SUFFIX
CASE 751
MARKING
DIAGRAMS*
8
8302C
ALYWG
G
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Figure 1. Block Diagram
© Semiconductor Components Industries, LLC, 2014
December, 2014 − Rev. 3
1
Publication Order Number:
NB3M8302C/D



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NB3M8302C
Figure 2. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin Number Name
1, 6 VDDO
2 VDD
3 CLK
4, 7 GND
5 Q1
8 Q0
Type
Output Power
Input and Core Power
LVCMOS/LVTTL Input
Ground
LVCMOS/LVTTL Output
LVCMOS/LVTTL Output
Description
Clock output Supply pin.
Input and Core Supply pin.
Clock Input. Internally pull−down.
Supply Ground.
LVCMOS/LVTTL Clock output.
LVCMOS/LVTTL Clock output.
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Condition
Min Max Unit
VDD, VDDO
VI
Tstg
qJA
Power Supply
Input Voltage
Storage Temperature
Thermal Resistance (Junction to Ambient)
SOIC−8
0 lfpm
500 lfpm
− 4.6 V
−0.5 VDD + 0.5 V V
−65
+150
_C
_C/W
80
55
qJC Thermal Resistance (Junction to Case)
(Note 1)
12−17
_C/W
Tsol
MSL
Wave Solder
Moisture Sensitivity
SOIC−8
3 sec
265 _C
Indefinite Time Out of Drypack
(Note 2)
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board – 2S2P (2 signal, 2 power)
2. For additional information, see Application Note AND8003/D.
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NB3M8302C
Table 3. DC OPERATING CHARACTERISTICS
(VDD = VDDO = 3.3 V±5%, VDD = 3.3 V±5%, VDDO = 2.5 V±5%; TA = −40°C to +85°C)
Symbol
Parameter
Condition
Min Typ Max Unit
RIN Input Pull−down Resistor (CLK Pin)
51 kW
CIN Input Capacitance
4 pF
ROUT
Output Impedance (Note 3)
5 7 12 W
CPD Power Dissipation Capacitance (per output)
VDD = VDDO = 3.465 V
22 pF
VDD = 3.465 V, VDDO = 2.625 V
16
VDD Core Supply Voltage
3.135 3.3 3.465
V
IIH Input High Current
VIN = VDD = 3.465 V
150 mA
IIL Input Low Current
VDD 3.465 V, VIN = 0.0 V
−0.5
mA
3. Outputs terminated with 50 W to VDDO/2. See Figure 4 for supply considerations.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. DC OPERATING CHARACTERISTICS (TA = −40°C to +85°C)
Symbol
Parameter
Condition
VDD = 3.3 V+5%, VDDO = 2.5 V+5%
VDDO
Output Supply Voltage
VOH Output HIGH Voltage
VOL Output LOW Voltage
VDD = VDDO = 3.3 V+5%
VDDO
Output Supply Voltage
VOH Output HIGH Voltage
VOL Output LOW Voltage
IOH = −16 mA
IOH = −100 mA
50 W to VDDO/2
IOL = 16 mA
IOL = 100 mA
50 W to VDDO/2
IOH = −16 mA
IOH = −100 mA
50 W to VDDO/2
IOL = 16 mA
IOL = 100 mA
50 W to VDDO/2
Min
2.375
2.1
2.2
1.8
3.135
2.9
2.9
2.6
Max
2.625
Unit
V
V
0.15
0.2
0.5
3.465
V
V
V
0.15 V
0.2
0.5
Table 5. DC OPERATING CHARACTERISTICS (TA = −40°C to +85°C; VDD = VDDO = 3.3 V±5%, VDD = 3.3 V±5%, VDDO = 2.5
V±5%)
Symbol
Parameter
Condition
Min Max Unit
IDD
IDDO
VIH
VIL
Quiescent Power Supply Current
Quiescent Power Supply Current
Input HIGH Voltage
Input LOW Voltage
No Load
No Load
2
−0.3
13
4
VDD + 0.3
1.3
mA
mA
V
V
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NB3M8302C
Table 6. AC CHARACTERISTICS (Note 4)
Symbol
Parameter
Condition
Min Typ Max Unit
TA = −405C to +855C; VDD = VDDO = 3.3 V+5%
FIN Input Frequency
tPLH Propagation Delay (Note 5)
tSKEW Output to Output Skew(Note 6)
Part to Part Skew (Note 6)
Fin = 200 MHz
200 MHz
1.9 3.1 ns
25 85 ps
250 800
tSKEWDC Output Duty Cycle (see Figure 3)
Fin v 133 MHz
133 MHz < Fin < 200 MHz
45
40
55 %
60
tr/tf Output rise and fall times (Note 7)
20% to 80%, RS = 33 W
250
800 ps
TA = −405C to +855C; VDD = 3.3 V+5%, VDDO = 2.5 V+5%
FIN Input Frequency
tPLH Propagation Delay (Note 5)
tSKEW Output to Output Skew(Note 6)
Part to Part Skew (Note 6)
Fin = 200 MHz
200 MHz
2.0 3.3 ns
25 85 ps
250 800
tSKEWDC Output Duty Cycle (see Figure 3)
Fin v 133 MHz
133 MHz < Fin < 200 MHz
45
40
55 %
60
tr/tf Output rise and fall times (Note 7)
20% to 80%, RS = 33 W
200
650 ps
4. Clock input with 50% duty cycle. Outputs terminated with 50 W to VDDO/2. See Figures 3 and 4.
5. Measured from VDD/2 of the input to VDDO/2 of the output.
6. Similar input conditions and the same supply voltages. Measured at VDDO /2. See Figures 3 and 4.
7. RS is Series Resistance at the clock outputs.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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