N01S818HA Datasheet PDF - ON Semiconductor

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N01S818HA
ON Semiconductor

Part Number N01S818HA
Description 1 Mb Ultra-Low Power Serial SRAM
Page 12 Pages


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N01S818HA
1 Mb Ultra-Low Power
Serial SRAM
Standard SPI Interface and Multiplex
DUAL and QUAD Interface
Overview
The ON Semiconductor serial SRAM family includes several
integrated memory devices including this 1 Mb serially accessed
Static Random Access Memory, internally organized as 128 K words
by 8 bits. The devices are designed and fabricated using
ON Semiconductor’s advanced CMOS technology to provide both
high-speed performance and low power. The devices operate with a
single chip select (CS) input and use a simple Serial Peripheral
Interface (SPI) protocol. In SPI mode, a single data-in (SI) and
data-out (SO) line is used along with the clock (SCK) to access data
within the device. In DUAL mode, two multiplexed data-in/data-out
(SIO0-SIO1) lines are used and in QUAD mode, four multiplexed
data-in/data-out (SIO0-SIO3) lines are used with the clock to access
the memory.
The devices can operate over a wide temperature range of 40°C to
+85°C and are available in a 8-lead TSSOP package.
Features
Power Supply Range: 1.7 to 2.2 V
Very Low Typical Standby Current < 1 mA
Very Low Operating Current < 10 mA
Simple Serial Interface
Single-bit SPI Access
DUAL-bit and QUAD-bit SPI-like Access
Flexible Operating Modes
Word Mode
Page Mode
Burst Mode (Full Array)
High Frequency Read and Write Operation
Clock Frequency 20 MHz
Built-in Write Protection (CS High)
High Reliability
Unlimited Write Cycles
These Devices are PbFree and are RoHS Compliant
Green TSSOP
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TSSOP8 3x4.4
CASE 948BH
PACKAGE CONFIGURATION
CS
SO / SIO1
NC / SIO2
VSS
1
2
3
4
8 VCC
7 HOLD / SIO3
6 SCK
5 SI / SIO0
ORDERING INFORMATION
Device
Package
Shipping
N01S818HAT22I TSSOP8
(PbFree)
N01S818HAT22IT TSSOP8
(PbFree)
100 Units / Tube
3000 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Table 1. DEVICE OPTIONS
Device / Part Number
N01S818HAT22I
Power Supply
1.7 V 2.2 V
© Semiconductor Components Industries, LLC, 2013
September, 2013 Rev. 0
Speed
20 MHz
1
Package
TSSOP8
Function
HOLD
Publication Order Number:
N01S818HA/D



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Table 2. PIN NAMES
Pin Name
CS
SCK
SI / SIO0
SO / SIO1
SC / SIO2
HOLD / SIO3
VCC
VSS
N01S818HA
Pin Function
Chip Select
Serial Clock
Data Input SPI mode
Data Input/Output 0 DUAL and QUAD mode
Data Output SPI mode
Data Input/Output 1 DUAL and QUAD mode
No Connect SPI and DUAL mode
Data Input/Output 2 QUAD mode
HOLD Input SPI and DUAL mode
Data Input/Output 3 QUAD mode
Power
Ground
SCK
CS
SI / SIO0
SO / SIO1
SIO2
HOLD / SIO3
Interface
Circuitry
Decode
Logic
Control
Logic
Data Flow
Circuitry
SRAM
Array
Figure 1. Functional Block Diagram
Table 3. CONTROL SIGNAL DESCRIPTIONS
Signal
Mode
Used
Name
Description
CS All Chip Select A low level selects the device and a high level puts the device in standby mode. If CS is brought
high during a program cycle, the cycle will complete and then the device will enter standby mode.
When CS is high, SO is in high-Z. CS must be driven low after power-up prior to any sequence
being started.
SCK
All Serial Clock Synchronizes all activities between the memory and controller. All incoming addresses, data and
instructions are latched on the rising edge of SCK. Data out is updated after the falling edge of
SCK.
SI SPI Serial Data In Receives instructions, addresses and data on the rising edge of SCK.
SO SPI Serial Data Out Data is transferred out after the falling edge of SCK.
HOLD SPI and
DUAL
Hold
A high level is required for normal operation. Once the device is selected and a serial sequence
is started, this input may be taken low to pause serial communication without resetting the serial
sequence. The pin must be brought low while SCK is low for immediate use. If SCK is not low,
the HOLD function will not be invoked until the next SCK high to low transition. The device must
remain selected during this sequence. SO is high-Z during the Hold time and SI and SCK are
inputs are ignored. To resume operations, HOLD must be pulled high while the SCK pin is low.
Lowering the HOLD input at any time will take to SO output to High-Z.
SIO0 - 1 DUAL
Serial Data
Input / Output
Receives instructions, addresses and data on the rising edge of SCK. Data is transferred out
after the falling edge of SCK. The instruction must be set after power-up to enable the DUAL
access mode.
SIO0 - 3 QUAD
Serial Data
Input / Output
Receives instructions, addresses and data on the rising edge of SCK. Data is transferred out
after the falling edge of SCK. The instruction must be set after power-up to enable the QUAD
access mode.
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N01S818HA
Basic Operation
The 1 Mb serial SRAM is designed to interface directly
with a standard Serial Peripheral Interface (SPI) common on
many standard micro-controllers in the default state. It may
also interface with other non-SPI ports by programming
discrete I/O lines to operate the device.
The serial SRAM contains an 8-bit instruction register and
is accessed via the SI pin. The CS pin must be low and the
HOLD pin must be high for the entire operation. Data is
sampled on the first rising edge of SCK after CS goes low.
If the clock line is shared, the user can assert the HOLD input
and place the device into a Hold mode. After releasing the
HOLD pin, the operation will resume from the point where
it was held. The Hold operation is only supported in SPI and
DUAL modes.
By programming the device through a command
instruction, the dual and quad access modes may be initiated.
In these modes, multiplexed I/O lines take the place of the
SPI SI and SO pins and along with the CS and SCK control
the device in a SPI-like, two bit (DUAL) and four bit
(QUAD) wide serial manner. Once the device is put into
either the DUAL or QUAD mode, the device will remain
operating in that mode until powered down or the Reset
Mode operation is programmed.
The following table contains the possible instructions and
formats. All instructions, addresses and data are transferred
MSB first and LSB last.
Table 4. INSTRUCTION SET
Instruction
READ
WRITE
EQIO
EDIO
RSTQIO
RDMR
WRMR
Command
03h
02h
38h
3Bh
FFh
05h
01h
Description
Read data from memory starting at selected address
Write (program) data to memory starting at selected address
Enable QUAD I/O access
Enable DUAL I/O access
Reset from QUAD and DUAL to SPI I/O access
Read mode register
Write mode register
DEVICE OPERATIONS
Read Operation
The serial SRAM Read operation is started by by enabling
CS low. First, the 8-bit Read instruction is transmitted to the
device through the SI (or SIO0-3) pin(s) followed by the
24-bit address with the 7 MSBs of the address being “don’t
care” bits and ignored. In SPI mode, after the READ
instruction and address bits are sent, the data stored at that
address in memory is shifted out on the SO pin after the
output valid time. Additional “dummy” clock cycles (four in
DUAL and two in QUAD) are required to follow the
instruction and address inputs prior to the data being driven
out on the SIO0-3 pins while operating in these two modes.
By continuing to provide clock cycles to the device, data
can continue to be read out of the memory array in
sequentially. The internal address pointer is automatically
incremented to the next higher address after each byte of
data is read out until the highest memory address is reached.
When the highest memory address is reached, 1FFFFh, the
address pointer wraps to the address 00000h. This allows the
read cycles to be continued indefinitely. All Read operations
are terminated by pulling CS high.
CS
SCK 0 1 2 3 4 5 6 7 8 9 10 11
29 30 31 32 33 34 35 36 37 38 39
Instruction
24bit address
SI 0 0 0 0 0 0 1 1 23 22 21 20
210
SO HighZ
Data Out
76543210
Figure 2. SPI Read Sequence (Single Byte)
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N01S818HA
CS
SCK 0 1 2 3 4 5 6 7 8 9 10 11
29 30 31 32 33 34 35 36 37 38 39
Instruction
24bit address
SI 0 0 0 0 0 0 1 1 23 22 21 20
210
Don’t Care
ADDR 1
Data Out from ADDR 1
SO HighZ
76543210
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Don’t Care
Data Out from ADDR 2
Data Out from ADDR 3
Data Out from ADDR n
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ... 7 6 5 4 3 2 1 0
Figure 3. SPI Read Sequence (Sequential Bytes)
CS
SCK
012345
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Instruction
24bit address
Data out
SIO[1:0]
C3 C2 C1 C0 A11 A10
MSB
A3 A2 A1 A0 X X X X H0 H0 L0 L0 H1 H1 L1 L1
MSB
Notes:
C[3:0] = 03h
H0 = 2 high order bits of data byte 0
L0 = 2 low order bits of data byte 0
H1 = 2 high order bits of data byte 1
L1 = 2 low order bits of data byte 1
Figure 4. DUAL Read Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Instruction
24bit address
Data out
SIO[3:0] C1 C0 A5 A4 A3 A2 A1 A0 X X H0 L0 H1 L1 H2 L2 H3 L3
MSB
MSB
Notes:
C[1:0] = 03h
H0 = 4 high order bits of data byte 0
L0 = 4 low order bits of data byte 0
H1 = 4 high order bits of data byte 1
L1 = 4 low order bits of data byte 1
Figure 5. QUAD Read Sequence
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