MN88413 Datasheet PDF - Panasonic Semiconductor

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MN88413
Panasonic Semiconductor

Part Number MN88413
Description Channel Decoder LSI for Digital Satellite Broadcast Reception
Page 5 Pages


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Digital Broadcast Reception LSI
MN88413
Channel Decoder LSI for Digital Satellite Broadcast Reception
s Overview
The MN88413 is a channel decoder LSI that integrates functions for digital satellite communications and broadcast
reception on a single chip.
The MN88413 supports both the Digital Video Broadcast (DVB) and the Digital Satellite System (DSS®) specifications.
It also supports a variable transport rate that can be set under program control using a fixed system clock frequency and
can implement a channel decoder with a minimal number of external components.
s Features
Can be used in systems conforming to DVB, in US DIRECTV® systems, and in single carrier per channel (SCPC)
communication systems.
Integrates a 2-channel A/D converter, a variable rate QPSK demodulator, and forward error correction
(FEC) on a single chip.
Supports transfer rates from 1 Mbps to 90 Mbps.
On-chip I/Q baseband signal offset voltage circuit and on-chip reference voltage circuit for the A/D and D/A converters.
On-chip PLL circuit
BER monitor function
I2C bus master circuit for tuner control
Supports LNB control clock and DiSEqC 1.0/1.1 and can output DiSEqC messages.
General-purpose input and output ports
On-chip boundary scan test circuit conforming to IEEE 1149.1
s Applications
Digital satellite broadcast receivers
Note: DSS® and DIRECTV® are registered trademarks of DIRECTV, Inc.
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MN88413
s Block Diagram
Digital Bloadcast Reception LSI
AGC DAC
NERRF
FSYNC
IIN ADC
QIN ADC
DO0-7
DEN
BYTCK
PSYNC
NPERR
SCK
OP0-2
PLL0-2
CPO
PLL Clock
reproduction
I2C I/F
(Master)
I2C I/F
TAP
controller
(JTAG)
LNB
controller DAC
LNBCK
LNB
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Digital Bloadcast Reception LSI
s Pin Assignment
TDI
TDO
TIN3
VSSC15
TIN4
VSS5
VDD5
VSSC16
TIN5
TIN6
TIN7
OP0
VSSC17
OP1
OP2
LNBCK
CKO
VSSC18
VSS6
VDD6
XO
VSSC19
XI
CSEL0
CSEL1
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
MN88413
50 PLL2
49 PLL1
48 PLL0
47 VSSC9
46 VDD2
45 VSS2
44 NERRF
43 VSSC8
42 FSYNC
41 SEL
40 NRST
39 SDA
38 VSSC7
37 SCL
36 VDD1
35 VSS1
34 MSDA
33 VSSC6
32 MSCL
31 SADR1
30 SADR0
29 VSSC5
28 TEST2
27 TEST1
26 TEST0
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MN88413
Digital Bloadcast Reception LSI
s Specifications Overview
QPSK demodulator
Data rate
: 1 Mbps to 90 Mbps
A/D converter resolution
: 6 bits
Linearity error
: ±0.5 LSB (typical)
Differential linearity error
: ±0.5 LSB (typical)
Input voltage level
: 1.5 V [p-p] (typical) [On-chip self-bias circuit]
Roll-off rate
: Switchable between the DVB and the DSS® specifications.
AFC range
: ± (<symbol rate>/8)
Synchronization establishment time
: 100 ms or less.
D/A converter used for LNB/AFC and AGC
Resolution
: 8 bits
Linearity error
: ±0.5 LSB (typical)
Differential linearity error
: ±0.5 LSB (typical)
Output voltage level
: 1.0 V [p-p] (typical) [0.0 V to 1.0 V]
Viterbi decoder
: Switchable between the DVB and the DSS® specifications.
: Automatic detection of encoding ratios in the range 1/2 to 7/8.
: Auto-synchronous operation
Frame synchronization detection, De-interleaver, Reed-Solomon decoding, and Energy dispersal
: Switchable between the DVB and the DSS® specifications.
PLL circuit
: Reference clock input frequency: 4 MHz to 30 MHz
CPU interface
: I2C bus interface
Supply voltage
: 3.3 V ±0.165 V
Power dissipation : 990 mW (typical) [at VDD = 3.3 V, 60 Mbps, R = 7/8]
Package
: QFP100-P-1818B (18 × 18 mm)
4



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MN88413 Channel Decoder LSI for Digital Satellite Broadcast Reception MN88413
Panasonic Semiconductor
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