ML9042-xx Datasheet PDF - LAPIS

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ML9042-xx
LAPIS

Part Number ML9042-xx
Description DOT MATRIX LCD CONTROLLER DRIVER
Page 30 Pages


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LAPIS Semiconductor
ML9042-xx
DOT MATRIX LCD CONTROLLER DRIVER
FEDL9042-01
Issue Date: Nov. 19, 2003
GENERAL DESCRIPTION
The ML9042 used in combination with an 8-bit or 4-bit microcontroller controls the operation of a character type
dot matrix LCD.
FEATURES
Easy interfacing with an 8-bit or 4-bit microcontroller
Switchable between serial and parallel interfaces
Dot-matrix LCD controller driver for a 5 8 dot font
Built-in circuit allowing automatic resetting at power-on
Built-in 17 common signal drivers and 100 segment signal drivers
Two built-in character generator ROMs each capable of generating 240 characters (5 8 dots)
The character generator ROM can be selected by bank switching (ROM1S) pin.
Creation of character patterns by programming: up to 8 character patterns (5 8 dots)
Built-in RC oscillation circuit using external or internal resistors
Program-selectable duties
When ABE bit is “L”: 1/8 duty (1 line: 5 8 dots), or 1/16 duty (2 lines: 5 8 dots)
When ABE bit is “H”: 1/9 duty (1 line: 5 8 dots + arbitrator), or 1/17 duty (2 lines: 5 8 dots + arbitrator)
Cursor display
Built-in bias dividing resistors to drive the LCD
Bi-directional transfer of segment outputs
Bi-directional transfer of common outputs
100-dot arbitrator display
Line display shifting
Built-in voltage multiplier circuit
Gold Bump Chip
ML9042-xx CVWA/DVWA
*xx indicates a character generator ROM code number.
*01, 11 and 21 indicate general character generator ROM code numbers.
CVWA indicates a bump chip with high hardness, and DVWA indicates a bump chip with low
hardness.
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BLOCK DIAGRAM
FEDL9042-01
ML9042-xx
Parallel-
serial converter
Segment Signal driver
100-bit latch
100-bit bi-directional shift register
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I/O CIRCUITS
VDD
P
N
Applied to pins T1, T2, and T3
FEDL9042-01
ML9042-xx
VDD
VDD
P
N
Applied to pins RW/SI, RS1, and
RS0/CSB
Applied to pins E/SHTB, SP, ROM1S, and BE
VDD
P
VDD
P
VDD
N
P
N
Output Enable signal
Applied to pins DB0(SO) to DB7
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LAPIS Semiconductor
FEDL9042-01
ML9042-xx
PIN DESCRIPTIONS
Symbol
RW/SI
RS0/CSB, RS1
E/SHTB
DB0(SO) to DB3
DB4 to DB7
OSC1
OSC2
OSCR3
OSCR5
COM1 to COM17
SEG1 to SEG100
Description
The input pin with a pull-up resistor to select Read (“H”) or Write (“L”) in the Parallel I/F
Mode.
The pin to input data in the Serial l/F Mode. Each instruction code and each data are
read in by the rising edge of the E/SHTB signal.
The input pins with a pull-up resistor to select a register in the Parallel l/F Mode.
RS1 RS0/CSB
Name of register
H H Data register
H L Instruction register
L L Expansion Instruction register
The RSo/CSB pin is configured as a chip enable input in the Serial I/F Mode. Setting
the RSo/CSB pin to “L” allows the I/F to be provided.
The input pin for data input/output between the CPU and the ML9042 and for
activating instructions in the Parallel l/F Mode.
This pin is configured as a shift clock input in the Serial I/F Mode. The data input to the
PW/SI pin is synchronized to the rising edge of the clock, and the data output from the
DB0(SO) pin is synchronized to the falling edge of the shift clock.
The input/output pins to transfer data of lower-order 4 bits between the CPU and the
ML9042 in the Parallel l/F Mode. The pins are not used for the 4-bit interface.
Only the DB0(SO) pin is configured as a data output in the Serial I/F Mode. Busy flag
& address and data are output synchronized to the falling edge of the E/SHTB signal.
These pins remain pulled up when data is not output.
Each pin is equipped with a pull-up resistor, so this pin should be open when not used.
The input/output pins to transfer data of upper 4 bits between the CPU and the
ML9042 in the Parallel l/F Mode. The pins are not used for the serial interface.
Each pin is equipped with a pull-up resistor, so this pin should be open in the Serial I/F
Mode when not used.
The clock oscillation pins required for LCD drive signals and the operation of the
ML9042 by instructions sent from the CPU.
To input external clock, the OSC1 pin should be used. The OSCR3, OSCR5, and OSC2
pins should be open.
To start oscillation with an external resistor, the resistor should be connected between
the OSC1 and OSC2 pins. The OSCR3 and OSCR5 pins should be open.
To start oscillation at 5 V using an internal resistor, the OSC2 and OSCR5 pins should
be short-circuited outside the ML9042. The OSC1 and OSCR3 pins should be open.
To start oscillation at 3 V using an internal resistor, the OSC2 and OSCR3 pins should
be short-circuited outside the ML9042. The OSC1 and OSCR5 pins should be open.
(The OSC2, OSCR3, and OSCR5 pins can also be short-circuited outside the ML9042,
and the OSC1 pin can be open.)
The LCD common signal output pins.
For 1/8 duty, non-selectable voltage waveforms are output via COM9 to COM17. For
1/9 duty, non-selectable voltage waveforms are output via COM10 to COM17. For 1/16
duty, a non-selectable voltage waveform is output via COM17.
The LCD segment signal output pins.
4/58



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