MCF53017 Datasheet PDF - Freescale Semiconductor


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MCF53017
Freescale Semiconductor

Part Number MCF53017
Description Version 3 ColdFire core
Page 30 Pages

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Freescale Semiconductor
Data Sheet: Advance Information
MCF5301x Data Sheet
Features
• Version 3 ColdFire® core with EMAC
• Up to 211 Dhrystone 2.1 MIPS @ 240 MHz
• 16 KBytes unified instruction/data cache
• 128 KBytes internal SRAM with standby power supply
support
• Crossbar switch technology (XBS) for concurrent access to
peripherals or RAM from multiple bus masters
• Enhanced Secure Digital Host Controller (eSDHC)
– Supports CE-ATA, SD Memory, miniSD Memory,
SDIO, miniSDIO, SD Combo, MMC, MMC plus, MMC
4x, and MMC RS cards
• Two ISO7816 smart card interfaces
• IC identification module
• Voice-band audio codec with integrated speaker,
microphone, headphone, and handset amplifiers
• 16- or 32-bit SDR, 16-bit DDR/mobile-DDR SDRAM
controller
• USB 2.0 On-the-Go controller
• USB host controller
• 2 10/100 Ethernet MACs
• Coprocessor for acceleration of the DES, 3DES, AES,
MD5, and SHA-1 algorithms
• Random number generator
• 16-channel DMA controller
• Synchronous serial interface
• 4 periodic interrupt timers
• 4 32-bit timers with DMA support
• Real-time clock (RTC) module with standby support
• DMA-supported serial peripheral interface (DSPI)
• 3 UARTs
• I2C bus interface
Document Numbewwr:w.MDaCtaSFhe5et34U0.c1om7
Rev. 5, 3/2010
MCF53017
LQFP–208
28 x 28
MAPBGA–256
17 x 17
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2010. All rights reserved.
Preliminary—Subject to Change Without Notice



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Table of Contents
1 MCF5301x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . .4
2 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .5
3.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.2 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.3 Supply Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . .6
3.3.1 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . .7
3.3.2 Power Down Sequence . . . . . . . . . . . . . . . . . . . .7
3.4 Power Consumption Specifications. . . . . . . . . . . . . . . . .8
4 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .9
4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.2 Pinout—208 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3 Pinout–256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . .18
5 Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . . . .19
5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .20
5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .21
5.4.1 PLL Power Filtering . . . . . . . . . . . . . . . . . . . . . .22
5.4.2 USB Power Filtering. . . . . . . . . . . . . . . . . . . . . .22
5.4.3 Supply Voltage Sequencing and Separation
Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.5 Oscillator and PLL Electrical Characteristics . . . . . . . .24
5.6 External Interface Timing Characteristics . . . . . . . . . . .25
5.6.1 FlexBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.7 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.7.1 SDR SDRAM AC Timing Characteristics. . . . . .27
5.7.2 DDR SDRAM AC Timing Characteristics . . . . .30
5.8 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . .32
5.9 Reset and Configuration Override Timing. . . . . . . . . . .33
5.10 USB On-The-Go . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.11 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 34
5.12 I2C Input/Output Timing Specifications . . . . . . . . . . . . 35
5.13 Fast Ethernet AC Timing Specifications . . . . . . . . . . . 37
5.13.1 Receive Signal Timing Specifications . . . . . . . 37
5.13.2 Transmit Signal Timing Specifications . . . . . . . 37
5.13.3 Asynchronous Input Signal Timing Specifications38
5.13.4 MII Serial Management Timing Specifications . 38
5.14 32-Bit Timer Module Timing Specifications . . . . . . . . . 39
5.15 DSPI Timing Specifications . . . . . . . . . . . . . . . . . . . . . 39
5.16 eSDHC Electrical Specifications . . . . . . . . . . . . . . . . . 41
5.16.1 eSDHC Timing . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.16.2 eSDHC Electrical DC Characterisics . . . . . . . . 42
5.17 SIM Electrical Specifications . . . . . . . . . . . . . . . . . . . . 43
5.17.1 General Timing Requirements . . . . . . . . . . . . . 43
5.17.2 Reset Sequence. . . . . . . . . . . . . . . . . . . . . . . . 44
5.17.3 Power Down Sequence . . . . . . . . . . . . . . . . . . 45
5.18 IIM/Fusebox Electrical Specifications . . . . . . . . . . . . . 46
5.19 Voice Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.19.1 Voice Codec ADC Specifications . . . . . . . . . . . 47
5.19.2 Voice Codec DAC Specifications . . . . . . . . . . . 51
5.20 Integrated Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.20.1 Speaker Amplifier . . . . . . . . . . . . . . . . . . . . . . . 55
5.20.2 Handset Amplifier . . . . . . . . . . . . . . . . . . . . . . . 56
5.20.3 Headphone Amplifier . . . . . . . . . . . . . . . . . . . . 57
5.20.4 Microphone Amplifier . . . . . . . . . . . . . . . . . . . . 57
5.21 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 58
5.22 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 60
6 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
MCF5301x Data Sheet, Rev. 5
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor



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16K
Instruction/
Data
Cache
128K
SRAM
Version 3 ColdFire Core
MCF53017
JTAG
Oscillator
PLL
EMAC
BDM
Hardware
Divide
CAU
2 FECs
USB Host
eDMA
eSDHC
USB OTG
Crossbar Switch (XBS)
Codec
Peripheral Bridge
IIM
Smart Card
Interface
DSPI
SSI
RNG
I2C
RTC &
Oscillator
GPIO
2 INTCs 2 EPORTs 3 UARTs
4 DMA
Timers
4 PITs
Splitter
FlexBus
SDRAM
Controller
BDM
CAU
DSPI
eDMA
eSDHC
EMAC
EPORT
FEC
GPIO
I2C
– Background debug module
– Cryptography acceleration unit
– DMA serial peripheral interface
– Enhanced direct memory access module
– Enhanced Secure Digital host controller
– Enchanced multiply-accumulate unit
– Edge port module
– Fast Ethernet Controller
– General purpose input/output module
– Inter-Integrated Circuit
LEGEND
IIM
INTC
IC identification module
Interrupt controller
JTAG
– Joint Test Action Group interface
PCI – Peripheral Component Interconnect
PIT – Programmable interrupt timers
PLL – Phase locked loop module
RNG
– Random number generator
RTC
– Real time clock
SSI – Synchronous serial interface
USB OTG – Universal Serial Bus On-the-Go controller
Freescale Semiconductor
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
3



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MCF5301x Family Comparison
1 MCF5301x Family Comparison
The following table compares the various device derivatives available within the MCF5301x family.
Table 1. MCF5301x Family Configurations
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Module
Version 3 ColdFire Core with EMAC (enhanced
multiply-accumulate unit)
Core (system) clock
Peripheral and external bus clock
(Core clock ÷ 3)
Performance (Dhrystone/2.1 MIPS)
Unified data/instruction cache
Static RAM (SRAM)
Voice-over-IP software
Cryptography acceleration unit (CAU)
Random number generator
Smart card interface (SIM)
Voice-band audio codec
Integrated audio amplifiers
IC identification module (IIM)
Enhanced Secure Digital host controller (eSDHC)
SDR/DDR SDRAM controller
FlexBus external interface
USB 2.0 On-the-Go
USB 2.0 Host
Synchronous serial interface (SSI)
Fast Ethernet controller (FEC)
UARTs
I2C
DSPI
Real-time clock
32-bit DMA timers
Watchdog timer (WDT)
Periodic interrupt timers (PIT)
Edge port module (EPORT)
Interrupt controllers (INTC)
2
3
4
4
2
••••••
up to 240 MHz
up to 80 MHz
—•
•—
•—
1 port
••
——
••
••
••
••
——
••
22
33
••
••
••
44
••
44
••
22
up to 211
16 Kbytes
128 Kbytes
•—
•—
•—
••
—•
2 Kbits
••
••
••
••
—•
••
22
33
••
••
••
44
••
44
••
22
—•
•—
•—
2 ports
••
••
••
••
••
••
••
••
22
33
••
••
••
44
••
44
••
22
2
3
4
4
2
MCF5301x Data Sheet, Rev. 5
4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor




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