MCF5249 Datasheet PDF - Freescale Semiconductor


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MCF5249
Freescale Semiconductor

Part Number MCF5249
Description Microprocessor
Page 30 Pages

MCF5249 datasheet pdf
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Freescale Semiconductor, Inc.
MCF5249
ColdFire® Integrated Microprocessor
User’s Manual
MCF5249UM/D
Rev. 4.0, 10/2003
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Freescale Semiconductor, Inc.
Document Revision History
Rev.
No.
1.0
2.0
3.0
4.0
Document Revision History
Date
Substantive Change(s)
10/2002
05/2003
08/2003
10/29/03
Chapter 21, Electrical Specifications
Chapter 21, Electrical Specifications
Chapter 4, QSPISEL bit
Chapter 21, Electrical Specifications
2
MCF5249UM
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Freescale Semiconductor, Inc.
Paragraph
Number
TABLE OF CONTENTS
Page
Number
SECTION 1
INTRODUCTION 1
1.1
1.2
1.3
1.4
1.5
1.6
1.6.1
1.6.2
1.6.3
1.6.4
1.6.5
1.6.6
1.6.7
1.6.8
1.6.9
1.6.10
1.6.11
1.6.12
1.6.13
1.6.14
1.6.15
1.6.16
1.6.17
1.6.18
1.6.19
1.6.20
1.6.21
1.6.22
1.6.23
1.6.24
1.6.25
MCF5249 Overview .............................................................................................................1-1
MCF5249 Feature Introduction ............................................................................................1-1
MCF5249 Block Diagram .....................................................................................................1-2
MCF5249 Feature Details ....................................................................................................1-3
160 MAPBGA Ball Assignments ..........................................................................................1-5
MCF5249 Functional Overview ...........................................................................................1-6
ColdFire V2 Core ............................................................................................................1-6
DMA Controller ...............................................................................................................1-6
Enhanced Multiply and Accumulate Module (EMAC) .....................................................1-6
Instruction Cache ............................................................................................................1-6
Internal 96-KByte SRAM ................................................................................................1-6
DRAM Controller ............................................................................................................1-7
System Interface .............................................................................................................1-7
External Bus Interface ....................................................................................................1-7
Serial Audio Interfaces ...................................................................................................1-7
IEC958 Digital Audio Interfaces ......................................................................................1-7
Audio Bus .......................................................................................................................1-7
CD-ROM Encoder/Decoder ............................................................................................1-8
Dual UART Module .........................................................................................................1-8
Queued Serial Peripheral Interface QSPI .......................................................................1-8
Timer Module ..................................................................................................................1-8
IDE and SmartMedia Interfaces .....................................................................................1-9
Analog/Digital Converter (ADC) ......................................................................................1-9
Flash Memory Card Interface .........................................................................................1-9
I2C Module ......................................................................................................................1-9
Chip-Selects ...................................................................................................................1-9
GPIO Interface ................................................................................................................1-9
Interrupt Controller ..........................................................................................................1-9
JTAG ............................................................................................................................1-10
System Debug Interface ...............................................................................................1-10
Crystal and On-chip PLL ..............................................................................................1-10
2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.4
2.5
2.6
2.7
SECTION 2
SIGNAL DESCRIPTION
Introduction ..........................................................................................................................2-1
GPIO ....................................................................................................................................2-4
MCF5249 BUS SIGNALS ....................................................................................................2-4
ADDRESS BUS ..............................................................................................................2-4
READ-WRITE CONTROL ..............................................................................................2-4
OUTPUT ENABLE ..........................................................................................................2-5
Data Bus .........................................................................................................................2-5
Transfer Acknowledge ....................................................................................................2-5
SDRAM Controller Signals ..................................................................................................2-5
CHIP SELECTS ...................................................................................................................2-5
ISA bus ................................................................................................................................2-6
bus buffer signals .................................................................................................................2-6
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Table of Contents
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TOC-1



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Table of Contents
Paragraph
Number
Freescale Semiconductor, Inc.
Page
Number
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.19.1
2.19.2
2.19.3
2.19.4
2.19.5
2.20
2.20.1
2.20.2
2.20.3
2.20.4
2.20.5
2.21
2.21.1
2.21.2
I2C Module Signals ..............................................................................................................2-6
Serial Module Signals ..........................................................................................................2-6
Timer Module Signals ..........................................................................................................2-7
Serial Audio Interface Signals ..............................................................................................2-7
Digital Audio Interface Signals .............................................................................................2-9
Subcode interface ................................................................................................................2-9
Analog to Digital Converter (ADC) .......................................................................................2-9
Secure Digital/ MemoryStick card Interface .......................................................................2-10
Queued Serial Peripheral Interface (QSPI) .......................................................................2-10
Crystal Trim .......................................................................................................................2-11
Clock Out ...........................................................................................................................2-11
Debug and Test Signals ....................................................................................................2-11
Test Mode .....................................................................................................................2-11
High Impedance ...........................................................................................................2-11
Processor Clock Output ................................................................................................2-11
Debug Data ..................................................................................................................2-11
Processor Status ..........................................................................................................2-11
BDM/JTAG Signals ............................................................................................................2-12
Test Clock .....................................................................................................................2-12
Test Reset/Development Serial Clock ..........................................................................2-12
Test Mode Select/Break Point ......................................................................................2-13
Test Data Input/Development Serial Input ....................................................................2-13
Test Data Output/Development Serial Output ..............................................................2-13
Clock and Reset signals ....................................................................................................2-14
Reset In ........................................................................................................................2-14
System Bus input ..........................................................................................................2-14
3.1
3.2
3.2.1
3.2.1.1
3.2.1.2
3.2.1.3
3.2.1.4
3.2.1.5
3.2.2
3.2.2.1
3.2.3
3.2.3.1
3.2.3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
SECTION 3
COLDFIRE CORE
Processor Pipelines .............................................................................................................3-1
Processor Register Description ...........................................................................................3-2
User Programming Model ...............................................................................................3-2
Data Registers (D0–D7) ............................................................................................3-2
Address Registers (A0–A6) .......................................................................................3-2
Stack Pointer (A7,SP) ................................................................................................3-2
Program Counter (PC) ...............................................................................................3-3
Condition Code Register (CCR) ................................................................................3-3
Enhanced Multiply Accumulate Module (EMAC) User Programming Model ..................3-4
EMAC Instruction Set Summary ................................................................................3-4
Supervisor Programming Model .....................................................................................3-5
Status Register (SR) ..................................................................................................3-6
Vector Base Register (VBR) ......................................................................................3-6
Exception Processing Overview ..........................................................................................3-7
Exception Stack Frame Definition ........................................................................................3-8
Processor Exceptions ........................................................................................................3-10
Access Error Exception ................................................................................................3-10
Address Error Exception ...............................................................................................3-10
Illegal Instruction Exception ..........................................................................................3-10
Divide By Zero ..............................................................................................................3-10
Privilege Violation .........................................................................................................3-11
Trace Exception ............................................................................................................3-11
TOC-2
MCF5249UM
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Go to: www.freescale.com
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