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The following revision history table summarizes changes contained in this document.
Description of Changes
Initial public release.
Added a footnote to RTI of Table 3.2; Added RTI description to Section 3.5.6;
Added a sentence "If active BDM mode is enabled in stop3, the internal RTI
clock is not available." to the Section 5.7 Real Time Interrupt.
Changed the Maximun Low Power of FBE and FEE in Table A-9 to 10 MHz.
Changed the Title of Table 13-2 from “IIC1A Register Field Descriptions” to
“IIC1F Register Field Descriptions”
Added 42-pin SDIP information.
Changed “However, when HGO=0, the maximum frequency is 8 MHz in FEE
and FBE modes.” to “However, when HGO=0, the maximum frequency is
10 MHz in FEE and FBE modes.” in Appendix B5.
Updated the “How to reach us” at backpage.
This product incorporates SuperFlash® technology licensed from SST.
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© Freescale Semiconductor, Inc., 2005-2008. All rights reserved.
MC9S08GB60A Data Sheet, Rev. 2