MC74HC4353 Datasheet PDF - Motorola

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MC74HC4353
Motorola

Part Number MC74HC4353
Description Analog Multiplexers/Demultiplexers
Page 13 Pages


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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Analog Multiplexers/
Demultiplexers with
Address Latch
High–Performance Silicon–Gate CMOS
The MC54/74HC4351, and MC54/74HC4353 utilize silicon–gate CMOS
technology to achieve fast propagation delays, low ON resistances, and low
OFF leakage currents. These analog multiplexers/demultiplexers control
analog voltages that may vary across the complete power supply range
(from VCC to VEE).
The Channel–Select inputs determine which one of the Analog Inputs/
Outputs is to be connected, by means of an analog switch, to the Common
Output/Input. The data at the Channel–Select inputs may be latched by
using the active–low Latch Enable pin. When Latch Enable is high, the latch
is transparent. When either Enable 1 (active low) or Enable 2 (active high) is
inactive, all analog switches are turned off.
The Channel–Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with LSTTL
outputs.
These devices have been designed so that the ON resistance (Ron) is
more linear over input voltage than Ron of metal–gate CMOS analog
switches.
For multiplexers/demultiplexers without latches, see the HC4051,
HC4052, and HC4053.
Fast Switching and Propagation Speeds
Low Crosstalk Between Switches
Diode Protection on All Inputs/Outputs
Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V
Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V
Improved Linearity and Lower ON Resistance than Metal–Gate Types
Low Noise
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: HC4351 — 222 FETs or 55.5 Equivalent Gates
HC4353 — 186 FETs or 46.5 Equivalent Gates
MC54/74HC4351
MC54/74HC4353
20
1
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
ORDERING INFORMATION
MC54HCXXXXJ
MC74HCXXXXN
MC74HCXXXXDW
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
MC54/74HC4351
X4 1
X6 2
20 VCC
19 X2
NC 3
18 X1
X4
17 X0
X7 5
16 X3
X5 6
15 A
ENABLE 1 7
14 NC
ENABLE 2 8
13 B
VEE 9
GND 10
12 C
11
LATCH
ENABLE
NC = NO CONNECTION
10/95
© Motorola, Inc. 1995
1 REV 6



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MC54/74HC4351 MC54/74HC4353
LOGIC DIAGRAM
MC54/74HC4351
Single–Pole, 8–Position Plus Common Off and Address Latch
ANALOG
INPUTS/OUTPUTS
X0 17
X1 18
X2 19
X3 16
X4 1
X5 6
X6 2
X7 5
MULTIPLEXER/
DEMULTIPLEXER
CHANNEL–SELECT
INPUTS
A
B
15
13
CHANNEL
ADDRESS
C 12 LATCH
LATCH ENABLE
SWITCH ENABLE 1
ENABLES ENABLE 2
11
7
8
4
COMMON
X OUTPUT/INPUT
PIN 20 = VCC
PIN 9 = VEE
PIN 10 = GND
PINS 3, 14 = NC
FUNCTION TABLE
MC54/74HC4351
Control Inputs
Enable
Select
1 2CBA
ON
Channel
(LE = H)*
L HLLL
L HLLH
L HLHL
L HLHH
L HHL L
L HHLH
L HHHL
L HHHH
H XXXX
X LXXX
X0
X1
X2
X3
X4
X5
X6
X7
None
None
X = don’t care
* When Latch Enable is low, the Channel
Selection is latched and the Channel
Address Latch does not change states.
BLOCK DIAGRAM
MC54/74HC4353
Triple Single–Pole, Double–Position Plus Common Off and Address Latch
X0 16
X1 17
X SWITCH
18 X
PIN ASSIGNMENT
Y1 1
20 VCC
Y0 2
Y1 1
Z0 6
Z1 4
Y SWITCH
Z SWITCH
19 Y
COMMON
OUTPUT/INPUT
5Z
Y0 2
NC 3
Z1 4
Z5
Z0 6
19 Y
18 X
17 X1
16 X0
15 A
CHANNEL–SELECT
INPUTS
A
B
C
15
13
12
CHANNEL
ADDRESS
LATCH
LATCH ENABLE
SWITCH ENABLE 1
ENABLES ENABLE 2
11
7
8
PIN 20 = VCC
PIN 9 = VEE
PIN 10 = GND
PINS 3, 14 = NC
NOTE:
This device allows independent control of each switch. Channel–Select
Input A controls the X Switch, Input B controls the Y Switch, and Input C
controls the Z Switch.
ENABLE 1 7
14 NC
ENABLE 2 8
13 B
VEE 9
GND 10
12 C
11
LATCH
ENABLE
NC = NO CONNECTION
FUNCTION TABLE
Control Inputs
Enable
Select
1 2CBA
On
Channel
(LE = H)*
L H L L L Z0 Y0 X0
L H L L H Z0 Y0 X1
L H L H L Z0 Y1 X0
L H L H H Z0 Y1 X1
L H H L L Z1 Y0 X0
L H H L H Z1 Y0 X1
L H H H L Z1 Y1 X0
L H H H H Z1 Y1 X1
H XXXX
None
X LXXX
None
X = Don’t Care
* When Latch Enable is low, the Channel Selection
is latched and the Channel Address Latch does not
change states.
MOTOROLA
2 High–Speed CMOS Logic Data
DL129 — Rev 6



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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMC54/74HC4351 MC54/74HC4353
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVEE
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎI
Positive DC Supply Voltage
(Ref. to GND)
(Ref. to VEE)
– 0.5 to + 7.0
– 0.5 to 14.0
Negative DC Supply Voltage (Ref. to GND)
– 7.0 to + 0.5
Analog Input Voltage
VEE – 0.5
to VCC + 0.5
DC Input Voltage (Ref. to GND)
DC Current Into or Out of Any Pin
– 1.5 to VCC + 1.5
± 25
V
V
V
V
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD Power Dissipation in Still Air,Plastic or Ceramic DIP†
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSOIC Package†
750
500
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature, 1 mm from Case for
10 Seconds
(Plastic DIP or SOIC Package)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Ceramic DIP)
– 65 to + 150
260
300
_C
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ* Maximum Ratings are those values beyond which damage to the device may occur.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
ranges indicated in the Recom-
mended Operating Conditions.
Unused digital input pins must be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused Analog I/O pins may be left
open or terminated. See Applica-
tions Information.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎFor high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Min Max Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC PositiveDCSupplyVoltage
(Ref. to GND) 2.0 6.0 V
(Ref. to VEE) 2.0 12.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVEE Negative DC Supply Voltage
(Ref. to GND) – 6.0 GND V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIS Analog Input Voltage
VEE VCC V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin Digital Input Voltage (Ref. to GND)
GND VCC V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIO*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTA
Static or Dynamic Voltage Across Switch
Operating Temperature, All Package Types
— 1.2 V
– 55 + 125 _C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtr, tf Input Rise and Fall Time,
Channel Select or Enable
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInputs (Figure 9a)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ* For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out of the switch may contain both VCC and switch input components.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎThe reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGuaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Test Conditions
VCC
V
v v– 55 to
25_C
85_C
125_C Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIH Minimum High–Level Input
Voltage, Channel–Select or
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎEnable Inputs
Ron = Per Spec
2.0 1.5 1.5 1.5
4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIL Maximum Low–Level Input
Voltage, Channel–Select or
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎEnable Inputs
Ron = Per Spec
2.0 0.3 0.3 0.3 V
4.5 0.9 0.9 0.9
6.0 1.2 1.2 1.2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin Maximum Input Leakage
Current, Channel–Select or
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎEnable Inputs
Vin = VCC or GND,
VEE = – 6.0 V
6.0 ± 0.1 ± 1.0 ± 1.0 µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC Maximum Quiescent Supply
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCurrent (per Package)
Channel Select = VCC or GND
Enables = VCC or GND
VIS = VCC or GND VEE = GND
VIO = 0 V
VEE = – 6.0
6.0
6.0
2
8
µA
20 40
80 160
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA



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MC54/74HC4351 MC54/74HC4353
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC ELECTRICAL CHARACTERISTICS AnalogSection
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Test Conditions
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRon Maximum“ON”Resistance
Vin = VIL or VIH
vVIS = VCC to VEE
IS 2.0 mA (Figures 1, 2)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRon
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIoff
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Maximum Off–Channel Leakage
Current, Any One Channel
Vin = VIL or VIH
vVIS = VCC or VEE (Endpoints)
IS 2.0 mA (Figures 1, 2)
Vin = VIL or VIH
vVIS = 1/2 (VCC – VEE)
IS 2.0 mA
Vin = VIL or VIH
VIO = VCC – VEE
Switch Off (Figure 3)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaximum Off–Channel Leakage Vin = VIL or VIH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCurrent, Common Channel
VIO = VCC – VEE
HC4351 Switch Off (Figure 4)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHC4353
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIon Maximum On–Channel Leakage Vin = VIL or VIH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCurrent, Channel to Channel
Switch to Switch = VCC – VEE
HC4351 (Figure 5)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHC4353
VCC
V
4.5
4.5
6.0
4.5
4.5
6.0
4.5
4.5
6.0
6.0
6.0
6.0
6.0
6.0
VEE
V
0.0
– 4.5
– 6.0
0.0
– 4.5
– 6.0
0.0
– 4.5
– 6.0
– 6.0
– 6.0
– 6.0
– 6.0
– 6.0
Guaranteed Limit
v v– 55 to
25_C
85_C
125_C
190 240 280
120 150 170
100 125 140
150 190 230
100 125 140
80 100 115
30 35 40
12 15 18
10 12 14
0.1 0.5 1.0
Unit
µA
0.2 2.0 4.0
0.1 1.0 2.0
µA
0.2 2.0 4.0
0.1 1.0 2.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎAC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Parameter
Maximum Propagation Delay, Channel–Select to Analog Output
(Figure 9)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Maximum Propagation Delay, Latch Enable to Analog Output
(Figure 12)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLZ,
tPHZ
Maximum Propagation Delay, Enable 1 or 2 to Analog Output
(Figure 11)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPZL,
tPZH
Maximum Propagation Delay, Enable 1 or 2 to Analog Output
(Figure 11)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCl/O
Maximum Input Capacitance
Maximum Capacitance Analog I/O
Common O/I: HC4351
HC4353
Feedthrough
Enable 1 = VIH, Enable 2 = VIL
VCC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
v v– 55 to
25_C
85_C
125_C
370 465 550
74 93 110
63 79 94
60 75 90
12 15 18
10 13 15
325 410 485
65 82 97
55 70 82
290 365 435
58 73 87
49 62 74
345 435 515
69 87 103
59 74 87
10 10 10
35 35 35
130 130 130
50 50 50
1.0 1.0 1.0
Unit
ns
ns
ns
ns
ns
pF
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package) (Figure 14)*
45 (HC4351)
45 (HC4353)
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
4 High–Speed CMOS Logic Data
DL129 — Rev 6



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