MC74HC4060A Datasheet PDF - Motorola

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MC74HC4060A
Motorola

Part Number MC74HC4060A
Description 14-Stage Binary Ripple Counter
Page 11 Pages


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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
14-Stage Binary Ripple
Counter With Oscillator
High–Performance Silicon–Gate CMOS
The MC54/74C4060A is identical in pinout to the standard CMOS
MC14060B. The device inputs are compatible with standard CMOS out-
puts; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 14 master–slave flip–flops and an oscillator
with a frequency that is controlled either by a crystal or by an RC circuit
connected externally. The output of each flip–flop feeds the next and the
frequency at each output is half of that of the preceding one. The state of
the counter advances on the negative–going edge of the Osc In. The
active–high Reset is asynchronous and disables the oscillator to allow
very low power consumption during stand–by operation.
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and may have to be gated with Osc Out 2 of the
HC4060A.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With JEDEC Standard No. 7A Requirements
Chip Complexity: 390 FETs or 97.5 Equivalent Gates
LOGIC DIAGRAM
Osc Out 1 Osc Out 2
10 9
Osc In 11
Reset 12
7 Q4
5 Q5
4 Q6
6 Q7
14 Q8
13 Q9
15 Q10
1 Q12
2 Q13
3 Q14
Pin 16 = VCC
Pin 8 = GND
MC54/74HC4060A
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
1
DT SUFFIX
TSSOP PACKAGE
CASE 748C–03
ORDERING INFORMATION
MC54HCXXXXAJ
MC74HCXXXXAN
MC74HCXXXXAD
MC74HCXXXXADT
Ceramic
Plastic
SOIC
TSSOP
Clock
X
FUNCTION TABLE
Reset
L
L
H
Output State
No Charge
Advance to Next State
All Outputs Are Low
Pinout: 16–Lead Plastic Package (Top View)
VCC Q10 Q8
16 15 14
Osc Osc
Q9 Reset Osc In Out 1 Out 2
13 12 11 10 9
12345678
Q12 Q13 Q14 Q6 Q5 Q7 Q4 GND
3/96
©10M/9o5torola, Inc. 1996
© Motorola, Inc. 1995
3–1 REV 1
3–1 REV 6



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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMC54/74HC4060A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5
± 20
V
V
mA
DC Output Current, per Pin
± 25 mA
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
TSSOP Package†
± 50
750
500
450
mA
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature, 1 mm from Case for 10 Seconds
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPlastic DIP, SOIC or TSSOP Package
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCeramic DIP
– 65 to + 150
260
300
_C
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ* Maximum Ratings are those values beyond which damage to the device may occur.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
v vVout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎFor high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Min Max Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC DC Supply Voltage (Referenced to GND)
2.5* 6.0 V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTA Operating Temperature Range, All Package Types
– 55 + 125 _C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtr, tf Input Rise/Fall Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ* The oscillator is guaranteed to function at 2.5 V minimum. However, parametrics are tested at
2.0 V by driving Pin 11 with an external clock source.
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
VIH
Parameter
Minimum High–Level Input Voltage
Condition
Vout = 0.1V or VCC –0.1V
|Iout| 20µA
VIL Maximum Low–Level Input Voltage Vout = 0.1V or VCC – 0.1V
|Iout| 20µA
VOH
Minimum High–Level Output
Voltage (Q4–Q10, Q12–Q14)
Vin = VIH or VIL
|Iout| 20µA
Vin =VIH or VIL
|Iout| 2.4mA
|Iout| 4.0mA
|Iout| 5.2mA
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
Guaranteed Limit
–55 to 25°C 85°C 125°C
1.50 1.50 1.50
2.10 2.10 2.10
3.15 3.15 3.15
4.20 4.20 4.20
0.50 0.50 0.50
0.90 0.90 0.90
1.35 1.35 1.35
1.80 1.80 1.80
1.9 1.9 1.9
4.4 4.4 4.4
5.9 5.9 5.9
2.48 2.34 2.20
3.98 3.84 3.70
5.48 5.34 5.20
Unit
V
V
V
MOTOROLA
3–2 High–Speed CMOS Logic Data
DL129 — Rev 6



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MC54/74HC4060A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
VCC
Guaranteed Limit
V –55 to 25°C 85°C 125°C Unit
VOL
Maximum Low–Level Output
Voltage (Q4–Q10, Q12–Q14)
Vin = VIH or VIL
|Iout| 20µA
2.0 0.1
4.5 0.1
6.0 0.1
0.1 0.1 V
0.1 0.1
0.1 0.1
Vin = VIH or VIL |Iout| 2.4mA 3.0 0.26 0.33 0.40
|Iout| 4.0mA 4.5 0.26 0.33 0.40
|Iout| 5.2mA 6.0 0.26 0.33 0.40
VOH
Minimum High–Level Output
Voltage (Osc Out 1, Osc Out 2)
Vin = VCC or GND
|Iout| 20µA
2.0 1.9
4.5 4.4
6.0 5.9
1.9 1.9 V
4.4 4.4
5.9 5.9
Vin =VCC or GND |Iout| 0.7mA 3.0 2.48 2.34 2.20
|Iout| 1.0mA 4.5 3.98 3.84 3.70
|Iout| 1.3mA 6.0 5.48 5.34 5.20
VOL
Maximum Low–Level Output
Voltage (Osc Out 1, Osc Out 2)
Vin = VCC or GND
|Iout| 20µA
2.0 0.1
4.5 0.1
6.0 0.1
0.1 0.1 V
0.1 0.1
0.1 0.1
Vin =VCC or GND |Iout| 0.7mA 3.0 0.26 0.33 0.40
|Iout| 1.0mA 4.5 0.26 0.33 0.40
|Iout| 1.3mA 6.0 0.26 0.33 0.40
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0 ±0.1 ±1.0 ±1.0 µA
ICC Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0µA
6.0 4
40 160 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
fmax
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
tPLH,
tPHL
Maximum Propagation Delay, Osc In to Q4*
(Figures 1 and 4)
tPLH,
tPHL
Maximum Propagation Delay, Osc In to Q14*
(Figures 1 and 4)
tPHL
Maximum Propagation Delay, Reset to Any Q
(Figures 2 and 4)
tPLH,
tPHL
Maximum Propagation Delay, Qn to Qn+1
(Figures 3 and 4)
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
–55 to 25°C 85°C
125°C
6.0 9.0 8.0
10 14 12
30 28 25
50 45 40
300 375 450
180 200 250
60 75 90
51 64 75
500 750 1000
350 450 600
250 275 300
200 220 250
195 245 300
75 100 125
39 49 61
33 42 53
75 95 125
60 75 95
15 19 24
13 16 20
Unit
MHz
ns
ns
ns
ns
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3
MOTOROLA



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MC54/74HC4060A
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) – continued
Symbol
Parameter
VCC
Guaranteed Limit
V –55 to 25°C 85°C
125°C
Unit
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0 75
3.0 27
4.5 15
6.0 13
95 110 ns
32 36
19 22
16 19
Cin Maximum Input Capacitance
10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
* For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tP = [93.7 + 59.3 (n–1)] ns
VCC = 4.5 V: tP = [30.25 + 14.6 (n–1)] ns
VCC = 3.0 V: tP = [61.5+ 34.4 (n–1)] ns
VCC = 6.0 V: tP = [24.4 + 12 (n–1)] ns
Typical @ 25°C, VCC = 5.0 V
CPD Power Dissipation Capacitance (Per Package)*
35 pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol
Parameter
VCC
Guaranteed Limit
V –55 to 25°C 85°C
125°C
Unit
trec Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0 100
3.0 75
4.5 20
6.0 17
125 150 ns
100 120
25 30
21 25
tw Minimum Pulse Width, Clock
(Figure 1)
2.0 75
3.0 27
4.5 15
6.0 13
95 110 ns
32 36
19 23
16 19
tw Minimum Pulse Width, Reset
(Figure 2)
2.0 75
3.0 27
4.5 15
6.0 13
95 110 ns
32 36
19 23
16 19
tr, tf Maximum Input Rise and Fall Times
(Figure 1)
2.0 1000
3.0 800
4.5 500
6.0 400
1000
800
500
400
1000
800
500
400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
3–4 High–Speed CMOS Logic Data
DL129 — Rev 6



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