MC74HC4060 Datasheet PDF - Motorola

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MC74HC4060
Motorola

Part Number MC74HC4060
Description 14-Stage Binary Ripple Counter
Page 10 Pages


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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
14-Stage Binary Ripple
Counter with Oscillator
High–Performance Silicon–Gate CMOS
The MC54/74HC4060 is identical in pinout to the standard CMOS
MC14060B. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 14 master–slave flip–flops and an oscillator with a
frequency that is controlled either by a crystal or by an RC circuit connected
externally. The output of each flip–flop feeds the next, and the frequency at
each output is half that of the preceding one. The state of the counter
advances on the negative–going edge of Osc In. The active–high Reset is
asynchronous and disables the oscillator to allow very low power consump-
tion during standby operation.
State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and may need to be gated with Osc Out 2 of the HC4060.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 390 FETs or 97.5 Equivalent Gates
LOGIC DIAGRAM
OSC OUT 1 OSC OUT 2
10 9
OSC IN 11
7 Q4
5 Q5
4 Q6
6 Q7
14 Q8
13 Q9
15 Q10
1 Q12
2 Q13
3 Q14
RESET 12
PIN 16 = VCC
PIN 8 = GND
MC54/74HC4060
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
ORDERING INFORMATION
MC54HCXXXXJ
MC74HCXXXXN
MC74HCXXXXDT
Ceramic
Plastic
TSSOP
PIN ASSIGNMENT
Q12 1
Q13 2
Q14 3
Q6 4
Q5 5
Q7 6
Q4 7
GND 8
16 VCC
15 Q10
14 Q8
13 Q9
12 RESET
11 OSC IN
10 OSC OUT 1
9 OSC OUT 2
Clock
X
FUNCTION TABLE
Reset
L
L
H
Output State
No Change
Advance to Next State
All Outputs are Low
10/95
© Motorola, Inc. 1995
1 REV 6



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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMC54/74HC4060
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 1.5 to VCC + 1.5
– 0.5 to VCC + 0.5
± 20
V
V
mA
DC Output Current, per Pin
± 25 mA
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic or Ceramic DIP†
TSSOP Package†
± 50
750
450
mA
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
– 65 to + 150
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or TSSOP Package)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Ceramic DIP)
260
300
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ* Maximum Ratings are those values beyond which damage to the device may occur.
_C
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
v vVout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Min Max Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC DC Supply Voltage (Referenced to GND)
2.5** 6.0 V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTA Operating Temperature, All Package Types
– 55 + 125 _C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtr, tf Input Rise and Fall Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ**The oscillator is guaranteed to function at 2.5 V minimum. However, parametrics are tested at
2.0 V by driving Pin 11 with an external clock source.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGuaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Test Conditions
VCC
V
v v– 55 to
25_C
85_C
125_C Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIH Minimum High–Level Input
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVoltage
vVout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
2.0 1.5 1.5 1.5
4.5 3.15 3.15 3.15
6.0 4.2 4.2 4 2
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIL MaximumLow–LevelInput
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVoltage
vVout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
2.0 0.3 0.3 0.3 V
4.5 0.9 0.9 0.9
6.0 1.2 1.2 1.2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOH
Minimum High–Level Output
Voltage (Q4–Q10, Q12–Q14)
vVin = VIH or VIL
|Iout| 20 µA
vVin = VIH or VIL |Iout| 4.0 mA
v|Iout| 5.2 mA
2.0
4.5
6.0
4.5
6.0
1.9
4.4
5.9
3.98
5.48
1.9 1.9
4.4 4.4
5.9 5.9
3.84 3.70
5.34 5.20
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOL
Maximum Low–Level Output
Voltage (Q4–Q10, Q12–Q14)
vVin = VIH or VIL
|Iout| 20 µA
vVin = VIH or VIL |Iout| 4.0 mA
v|Iout| 5.2 mA
2.0
4.5
6.0
4.5
6.0
0.1
0.1
0.1
0.26
0.26
0.1 0.1
0.1 0.1
0.1 0.1
0.33 0.40
0.33 0.40
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2 High–Speed CMOS Logic Data
DL129 — Rev 6



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MC54/74HC4060
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) (Continued)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOH
Parameter
Minimum High–Level Output
Voltage (Osc Out 1, Osc Out 2)
Test Conditions
vVin = VCC or GND
IIoutI 20 µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎvVin=VCCorGNDIIoutI 1.0mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎvIIoutI 1.3mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOL
vMaximum Low–Level Output
Voltage (Osc Out 1, Osc Out 2)
Vin = VCC or GND
IIoutI 20 µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎvVin=VCCorGNDIIoutI 1.0mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎvIIoutI 1.3mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin Maximum Input Leakage Current Vin = VCC or GND
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTE: Information on typical parametric values can be found in Chapter 4.
VCC
V
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎAC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎfmax
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Maximum Propagation Delay, Osc In to Q4*
(Figures 1 and 4)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Maximum Propagation Delay, Osc In to Q14*
(Figures 1 and 4)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Maximum Propagation Delay, Reset to Any Q
(Figures 2 and 4)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
tPHL
Maximum Propagation Delay, QN to QN + 1
(Figures 3 and 4)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTES:
Maximum Input Capacitance
VCC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
v v– 55 to
25_C
85_C
125_C
1.9 1.9 1.9
4.4 4.4 4.4
5.9 5.9 5.9
3.98 3.84 3.70
5.48 5.34 5.20
0.1 0.1 0.1
0.1 0.1 0.1
0.1 0.1 0.1
0.26 0.33 0.40
0.26 0.33 0.40
± 0.1
± 1.0
± 1.0
8 80 160
Unit
V
V
µA
µA
Guaranteed Limit
v v– 55 to
25_C
85_C
125_C
5.0 4.0 3.4
25 20 17
29 24 20
530 665 795
106 133 159
91 114 135
1600
320
272
2000
400
344
2400
480
408
240 300 360
48 60 72
41 51 61
125 155 190
25 31 38
21 26 32
75 95 110
15 19 22
13 16 19
10 10 10
Unit
MHz
ns
ns
ns
ns
ns
pF
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
* For TA = 25_C and CL = 50 pF, typical propagation delay from Osc In to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tP = [205 + 107.5(N – 1)] ns
VCC = 4.5 V: tP = [41 + 21.5(N – 1)] ns
VCC = 6.0 V: tP = [35 + 18.3(N – 1)] ns
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*
35 pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA



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MC54/74HC4060
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTIMING REQUIREMENTS (Inputtr=tf=6ns)
Guaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
VCC
V
v v– 55 to
25_C
85_C
125_C Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtrec Minimum Recovery Time, Reset Inactive to Osc In*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figure 2)
2.0 100 125 150 ns
4.5 20 25 30
6.0 17 21 26
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtw Minimum Pulse Width, Osc In
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figure 1)
2.0 80
4.5 16
6.0 14
100 120 ns
20 24
17 20
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtw Minimum Pulse Width, Reset
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figure 2)
2.0 80
4.5 16
6.0 14
100 120 ns
20 24
17 20
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtr, tf Maximum Input Rise and Fall Times
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figure 1)
2.0 1000
4.5 500
6.0 400
1000
500
400
1000
500
400
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
* Osc In driven with external clock.
PIN DESCRIPTIONS
INPUTS
Osc In (Pin 11)
Negative–edge triggering clock input. A high–to–low tran-
sition on this input advances the state of the counter. Osc In
may be driven by an external clock source.
Reset (Pin 12)
Active–high reset. A high level applied to this input asynch-
ronously resets the counter to its zero state (forcing all Q out-
puts low) and disables the oscillator.
OUTPUTS
Q4 – Q10, Q12 – Q14 (Pins 7, 5, 4, 6, 14, 13, 15, 1, 2, 3)
Active–high outputs. Each QN output divides the oscillator
frequency by 2N. The user should note that Q1, Q2, Q3, and
Q11 are not available as outputs.
Osc Out 1, Osc Out 2 (Pins 10, 9)
Oscillator outputs. These pins are used in conjunction with
Osc In and the external components to form an oscillator.
(See Figures 4 and 5). When Osc In is being driven with an
external clock source, Osc Out 1 and Osc Out 2 must be left
open circuited. With the crystal oscillator configuration in Fig-
ure 6, Osc Out 2 must be left open circuited.
OSC IN
Q1
tf
90%
50%
10%
tr
90%
50%
10%
tw
1/fmax
tPLH
tPHL
tTLH tTHL
Figure 1.
SWITCHING WAVEFORMS
VCC RESET
GND
Q
CLOCK
tw
50%
tPHL
50%
trec
50%
Figure 2.
VCC
GND
VCC
GND
TEST POINT
QN 50%
QN + 1
tPLH
50%
tPHL
Figure 3.
VCC
GND
DEVICE
UNDER
TEST
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 4. Test Circuit
MOTOROLA
4 High–Speed CMOS Logic Data
DL129 — Rev 6



MC74HC4060 datasheet pdf
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