MC54HCT32A Datasheet PDF - Motorola

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MC54HCT32A
Motorola

Part Number MC54HCT32A
Description Octal 2-Input OR Gate
Page 5 Pages


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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-Input OR Gate with
LSTTL-Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC54/74HCT32A may be used as a level converter for interfacing
TTL or NMOS outputs to High–Speed CMOS inputs.
The HCT32A is identical in pinout to the LS32.
Output Drive Capability: 10 LSTTL Loads
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 64 FETs or 16 Equivalent Gates
LOGIC DIAGRAM
A1 1
B1 2
A2 4
B2 5
A3 9
B3 10
A4 12
B4 13
3 Y1
6 Y2
Y=A+B
8 Y3
11 Y4
PIN 14 = VCC
PIN 7 = GND
MC54/74HCT32A
14
1
J SUFFIX
CERAMIC PACKAGE
CASE 632–08
14
1
14
1
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
D SUFFIX
SOIC PACKAGE
CASE 751A–03
ORDERING INFORMATION
MC54HCTXXAJ
MC74HCTXXAN
MC74HCTXXAD
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
A1 1
B1 2
Y1 3
A2 4
B2 5
Y2 6
GND 7
14 VCC
13 B4
12 A4
11 Y4
10 B3
9 A3
8 Y3
FUNCTION TABLE
Inputs
AB
LL
LH
HL
HH
Output
Y
L
H
H
H
10/95
© Motorola, Inc. 1995
1 REV 6



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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMC54/74HCT32A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 1.5 to VCC + 1.5
– 0.5 to VCC + 0.5
± 20
DC Output Current, per Pin
± 25
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
± 50
750
500
V
V
V
mA
mA
mA
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature, 1 mm from Case for 10 Seconds
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Plastic DIP)
(Ceramic DIP)
– 65 to + 150
260
300
_C
_C
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ*Maximum Ratings are those values beyond which damage to the device may occur.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
v vVout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎFor high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout
TA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtr, tf
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
Min Max Unit
4.5 5.5 V
0 VCC V
– 55 + 125 _C
0 500 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC ELECTRICAL CHARACTERISTICS FOR THE MC54/74HCT32A (Voltages Referenced to GND)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Test Conditions
VCC
Volts
Guaranteed Limits
– 55 to 25_C
v 85_C
v 125_C
Min Max Min Max Min Max
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎvVIH MinimumHigh–Level
Vout = 0.1 V or VCC – 0.1 V
4.5 2.0
2.0
2.0
Input Voltage
|Iout| 20 µA
5.5 2.0 2.0 2.0
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
Maximum Low–Level
Input Voltage
Minimum High–Level
Output Voltage
Maximum Low–Level
Output Voltage
Maximum Input Leakage
Current
vVout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
vVin = VIH or VIL
|Iout| 20 µA
vVin = VIH or VIL
|Iout| 4.0 mA
vVin = VIH or VIL
|Iout| 20 µA
vVin = VIH or VIL
|Iout| 4.0 mA
Vin = VCC or GND
4.5 0.8 0.8 0.8
5.5 0.8 0.8 0.8
4.5 4.4 4.4 4.4
5.5 5.4 5.4 5.4
V
V
5.5 3.98
3.84
3.7
4.5 0.1 0.1 0.1
5.5 0.1 0.1 0.1
V
4.5 0.26 0.33 0.4
5.5
± 0.1
± 1.0
± 1.0 µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC Maximum Quiescent Sup- Vin = VCC or GND
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎply Current (per Package) Iout = 0 µA
5.5 1.0 10 40 µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55_C
25_C to
125_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC Additional Quiescent
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSupply Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 µA
5.5
2.9 2.4
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2 High–Speed CMOS Logic Data
DL129 — Rev 6



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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMC54/74HCT32A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎAC CHARACTERISTICS FOR THE MC54/74HCT32A (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGuaranteed Limits
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 to 25_C
v 85_C
v 125_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Fig. Min Max Min Max Min Max Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH, Maximum Propagation Delay, Input A or B to Output Y
1, 2
20
25
30 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTLH, Maximum Output Transition Time, Any Output
tTHL
1, 2 15 19 22 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCin Maximum Input Capacitance
10 10 10 pF
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD Power Dissipation Capacitance (Per Gate)*
15 pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
INPUT
A OR B
OUTPUT Y
tr
90%
1.3 V
10%
tPLH
90%
1.3 V
10%
tTLH
tf
tPHL
Figure 1. Switching Waveforms
3.0 V
GND
tTHL
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 2. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/4 OF THE DEVICE)
A
Y
B
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA



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MC54/74HCT32A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC DIP PACKAGE
-A- CASE 632–08
ISSUE Y
14 8
-B-
17
CL
-T-
SEATING
PLANE
F
GN
D 14 PL
0.25 (0.010) M T A S
K
M
J 14 PL
0.25 (0.010) M T B S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMESNION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.94
B 0.245 0.280 6.23 7.11
C 0.155 0.200 3.94 5.08
D 0.015 0.020 0.39 0.50
F 0.055 0.065 1.40 1.65
G 0.100 BSC
2.54 BSC
J 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC
7.62 BSC
M 0° 15° 0° 15°
N 0.020 0.040 0.51 1.01
14
1
A
F
HG
8
B
7
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
C
N
SEATING
PLANE
D
K
L
J
M
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC
2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC
7.62 BSC
M 0_ 10_ 0_ 10_
N 0.015 0.039 0.39 1.01
–A–
14
1
G
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
8
–B–
7
P 7 PL
0.25 (0.010) M B M
C R X 45°
F
SEATING
PLANE
D 14 PL
K
0.25 (0.010) M T B S
AS
M
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0° 7°
0° 7°
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
MOTOROLA
4 High–Speed CMOS Logic Data
DL129 — Rev 6



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