MC54HCT241A Datasheet PDF - Motorola

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MC54HCT241A
Motorola

Part Number MC54HCT241A
Description Octal 3-State Noninverting Buffer/Line Driver/Line Receiver
Page 7 Pages


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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Noninverting
Buffer/Line Driver/
Line Receiver with
LSTTL-Compatible Inputs
High–Performance Silicon–Gate CMOS
MC54/74HCT241A
20
1
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
The MC54/74HCT241A is identical in pinout to the LS241. This device
may be used as a level converter for interfacing TTL or NMOS outputs to
High–Speed CMOS inputs. The HCT241A is an octal noninverting buffer/line
driver/line receiver designed to be used with 3–state memory address
drivers, clock drivers, and other bus–oriented systems. The device has
non–inverted outputs and two output enables. Enable A is active–low and
Enable B is active–high.
The HCT241A is similar in function to the HCT244. See also HCT240.
Output Drive Capability: 15 LSTTL Loads
TTL/NMOS–Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1 µA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 118 FETs or 29.5 Equivalent Gates
LOGIC DIAGRAM
A1 2
A2 4
A3 6
DATA INPUTS
A4 8
B1 11
18 YA1
16 YA2
14 YA3
12 YA4
NONINVERTING
9 YB1 OUTPUTS
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
ORDERING INFORMATION
MC54HCTXXXAJ Ceramic
MC74HCTXXXAN Plastic
MC74HCTXXXADW SOIC
PIN ASSIGNMENT
ENABLE A 1
A1 2
YB4 3
A2 4
YB3 5
A3 6
YB2 7
A4 8
YB1 9
GND 10
20 VCC
19 ENABLE B
18 YA1
17 B4
16 YA2
15 B3
14 YA3
13 B2
12 YA4
11 B1
B2 13
B3 15
B4 17
OUTPUT ENABLE A 1
ENABLES ENABLE B 19
7 YB2
5 YB3
3 YB4
PIN 20 = VCC
PIN 10 = GND
FUNCTION TABLE
Inputs
Enable A A
Output
YA
LLL
L HH
HXZ
Inputs
Enable B B
HL
HH
LX
Output
YB
L
H
Z
Z = high impedance
X = don’t care
2/97
© Motorola, Inc. 1997
1
REV 7



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MC54/74HCT241A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5
± 20
DC Output Current, per Pin
± 35
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
± 75
750
500
V
V
V
mA
mA
mA
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Ceramic DIP)
– 65 to + 150
260
300
_C
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
v vVout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtr, tf
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
Min Max Unit
4.5 5.5 V
0 VCC V
– 55 + 125 _C
0 500 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIOZ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC
Parameter
Minimum High–Level Input
Voltage
Maximum Low–Level Input
Voltage
Minimum High–Level Output
Voltage
Maximum Low–Level Output
Voltage
Maximum Input Leakage Current
Maximum Three–State
Leakage Current
Maximum Quiescent Supply
Current (per Package)
Test Conditions
vVout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
vVout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
vVin = VIH or VIL
|Iout| 20 µA
vVin = VIH or VIL
|Iout| 6 mA
vVin = VIH or VIL
|Iout| 20 µA
vVin = VIH or VIL
|Iout| 6 mA
Vin = VCC or GND
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
Vin = VCC or GND
Iout = 0 µA
VCC
V
4.5
5.5
4.5
5.5
4.5
5.5
4.5
4.5
5.5
4.5
5.5
5.5
5.5
Guaranteed Limit
v v– 55 to
25_C
85_C
125_C
222
222
0.8 0.8 0 8
0.8 0.8 0.8
4.4 4.4 4.4
5.4 5.4 5.4
3.98 3.84
0.1 0.1
0.1 0.1
3.7
0.1
0.1
0.26
± 0.1
± 0.5
0.33
± 1.0
± 5.0
0.4
± 1.0
± 10
4 40 160
Unit
V
V
V
V
µA
µA
µA
MOTOROLA
2 High–Speed CMOS Logic Data
DL129 — Rev 6



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MC54/74HCT241A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC
Additional Quiescent Supply
Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 µA
5.5
–55_C
2.9
25_C to 125_C
2.4
mA
NOTES:
1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
2. Total Supply Current = ICC + Σ∆ICC.
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA



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MC54/74HCT241A
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGuaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
– 55 to
25_C
v v85_C
125_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
tPHL
Maximum Propagation Delay, A to YA or B to YB
(Figures 1 and 3)
23 29 35
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLZ,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHZ
Maximum Propagation Delay, Output Enable to YA or YB
(Figures 2 and 4)
30 38 45
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPZL,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPZH
Maximum Propagation Delay, Output Enable to YA or YB
(Figures 2 and 4)
26 33 39
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
12 15 18
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCin MaximumInputCapacitance
10 10 10
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCout
Maximum Three–State Output Capacitance (Output in High–Impedance
15
15
15
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎState)
Unit
ns
ns
ns
ns
pF
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Enabled Output)*
55 pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
INPUT
A OR B
tr
tPLH
OUTPUT
YA OR YB
2.7 V
1.3 V
0.3 V
90%
1.3 V
10%
tTLH
Figure 1.
SWITCHING WAVEFORMS
ENABLE A
1.3 V
tf
3V
GND
tPHL
tTHL
ENABLE B
OUTPUT Y
OUTPUT Y
1.3 V
tPZL tPLZ
1.3 V
tPZH tPHZ
1.3 V
Figure 2.
3V
GND
3V
GND
HIGH
IMPEDANCE
10% VOL
90% VOH
HIGH
IMPEDANCE
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 k
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
* Includes all probe and jig capacitance
Figure 3. Test Circuit
* Includes all probe and jig capacitance
Figure 4. Test Circuit
MOTOROLA
4 High–Speed CMOS Logic Data
DL129 — Rev 6



MC54HCT241A datasheet pdf
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MC54HCT241A Octal 3-State Noninverting Buffer/Line Driver/Line Receiver MC54HCT241A
Motorola
MC54HCT241A pdf

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