MC54HC541A Datasheet PDF - Motorola

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MC54HC541A
Motorola

Part Number MC54HC541A
Description Octal 3-State Non-Inverting Buffer/Line Driver/Line Receiver
Page 6 Pages


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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Non-Inverting
Buffer/Line Driver/
Line Receiver
High–Performance Silicon–Gate CMOS
The MC54/74HC541A is identical in pinout to the LS541. The device
inputs are compatible with Standard CMOS outputs. External pullup
resistors make them compatible with LSTTL outputs.
The HC541A is an octal non–inverting buffer/line driver/line receiver
designed to be used with 3–state memory address drivers, clock drivers, and
other bus–oriented systems. This device features inputs and outputs on
opposite sides of the package and two ANDed active–low output enables.
The HC541A is similar in function to the HC540A, which has inverting
outputs.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6V
Low Input Current: 1µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 134 FETs or 33.5 Equivalent Gates
MC54/74HC541A
20
1
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
Ceramic
Plastic
SOIC
Data
Inputs
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
LOGIC DIAGRAM
18
Y1
17
Y2
16
Y3
15
Y4
14
Y5
Non–Inverting
Outputs
13
Y6
FUNCTION TABLE
Inputs
OE1 OE2 A
Output Y
LLL
L LH
HXX
XHX
L
H
Z
Z
Z = High Impedance
X = Don’t Care
8
A7
12
Y7
9
A8
11
Y8
Output
Enables
OE1 1
OE2
19
PIN 20 = VCC
PIN 10 = GND
Pinout: 20–Lead Packages (Top View)
VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7
20 19 18 17 16 15 14 13 12
Y8
11
10/95
© Motorola, Inc. 1995
1 2 3 4 5 6 7 8 9 10
OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND
3–1 REV 1



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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMC54/74HC541A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5
± 20
V
V
mA
DC Output Current, per Pin
± 35 mA
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
± 75
750
500
mA
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP or SOIC Package
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCeramic DIP)
– 65 to + 150
260
300
_C
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
v vVout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Min Max Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtr, tf
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature Range, All Package Types
Input Rise/Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
2.0
0
– 55
0
0
0
6.0
VCC
+ 125
1000
500
400
V
V
_C
ns
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
VCC
Guaranteed Limit
V –55 to 25°C 85°C 125°C Unit
VIH Minimum High–Level Input Voltage Vout = 0.1V
|Iout| 20µA
2.0
1.50
1.50 1.50
V
3.0 2.10 2.10 2.10
4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum Low–Level Input Voltage Vout = VCC – 0.1V
|Iout| 20µA
2.0
0.50
0.50 0.50
V
3.0 0.90 0.90 0.90
4.5 1.35 1.35 1.35
6.0 1.80 1.80 1.80
VOH
Minimum High–Level Output
Voltage
Vin = VIL
|Iout| 20µA
2.0 1.9
4.5 4.4
6.0 5.9
1.9 1.9 V
4.4 4.4
5.9 5.9
Vin = VIL
|Iout| 3.6mA 3.0 2.48 2.34 2.20
|Iout| 6.0mA 4.5 3.98 3.84 3.70
|Iout| 7.8mA 6.0 5.48 5.34 5.20
VOL
Maximum Low–Level Output
Voltage
Vin = VIH
|Iout| 20µA
2.0 0.1
4.5 0.1
6.0 0.1
0.1 0.1 V
0.1 0.1
0.1 0.1
Vin = VIH
|Iout| 3.6mA 3.0 0.26 0.33 0.40
|Iout| 6.0mA 4.5 0.26 0.33 0.40
|Iout| 7.8mA 6.0 0.26 0.33 0.40
MOTOROLA
3–2 High–Speed CMOS Logic Data
DL129 — Rev 6



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MC54/74HC541A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
VCC
Guaranteed Limit
V –55 to 25°C 85°C 125°C Unit
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0 ±0.1 ±1.0 ±1.0 µA
IOZ Maximum Three–State Leakage
Output in High Impedance State
6.0
±0.5
±5.0 ±10.0 µA
Current
Vin = VIL or VIH
Vout = VCC or GND
ICC Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0µA
6.0 4
40 160 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
VCC
Guaranteed Limit
V –55 to 25°C 85°C
125°C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
2.0 80
3.0 30
4.5 18
6.0 15
100 120 ns
40 55
23 28
20 25
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0 110
3.0 45
4.5 25
6.0 21
140 165 ns
60 75
31 38
26 31
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0 110
3.0 45
4.5 25
6.0 21
140 165 ns
60 75
31 38
26 31
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0 60
3.0 22
4.5 12
6.0 10
75 90 ns
28 34
15 18
13 15
Cin
Cout
Maximum Input Capacitance
Maximum Three–State Output Capacitance (Output in High
Impedance State)
10 10 10 pF
15 15 15 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD Power Dissipation Capacitance (Per Buffer)*
35 pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
SWITCHING WAVEFORMS
tr
INPUT A
tPLH
90%
50%
10%
OUTPUT Y
50%
10%
tTLH
90%
tf
VCC OE1 or OE2
GND
tPHL
OUTPUT Y
OUTPUT Y
tTHL
Figure 1.
50%
tPZL tPLZ
50%
tPZH tPHZ
50%
50%
10%
90%
Figure 2.
VCC
GND
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3
MOTOROLA



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MC54/74HC541A
DEVICE
UNDER
TEST
TEST
POINT
OUTPUT
CL*
TEST CIRCUITS
DEVICE
UNDER
TEST
TEST
POINT
OUTPUT
1k
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ and tPZH.
*Includes all probe and jig capacitance
Figure 3.
*Includes all probe and jig capacitance
Figure 4.
PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8,
9) — Data input pins. Data on these pins appear in non–in-
verted form on the corresponding Y outputs, when the out-
puts are enabled.
CONTROLS
OE1, OE2 (PINS 1, 19) — Output enables (active–low).
When a low voltage is applied to both of these pins, the out-
puts are enabled and the device functions as an non–invert-
ing buffer. When a high voltage is applied to either input, the
outputs assume the high impedance state.
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11) — Device outputs. Depending upon the state of
the output enable pins, these outputs are either non–invert-
ing outputs or high–impedance outputs.
LOGIC DETAIL
To 7 Other
Buffers
INPUT A
One of Eight
Buffers
VCC
OUTPUT Y
OE1
OE2
MOTOROLA
3–4 High–Speed CMOS Logic Data
DL129 — Rev 6



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MC54HC541A Octal 3-State Non-Inverting Buffer/Line Driver/Line Receiver MC54HC541A
Motorola
MC54HC541A pdf

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