MC54HC390A Datasheet PDF - Motorola

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MC54HC390A
Motorola

Part Number MC54HC390A
Description Dual 4-Stage Binary Ripple Counter
Page 9 Pages


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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Product Preview
Dual 4-Stage Binary
Ripple Counter with
÷ 2 and ÷ 5 Sections
High–Performance Silicon–Gate CMOS
The MC54/74HC390A is identical in pinout to the LS390. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device consists of two independent 4–bit counters, each composed
of a divide–by–two and a divide–by–five section. The divide–by–two and
divide–by–five counters have separate clock inputs, and can be cascaded to
implement various combinations of ÷ 2 and/or ÷ 5 up to a ÷ 100 counter.
Flip–flops internal to the counters are triggered by high–to–low transitions
of the clock input. A separate, asynchronous reset is provided for each 4–bit
counter. State changes of the Q outputs do not occur simultaneously
because of internal ripple delays. Therefore, decoded output signals are
subject to decoding spikes and should not be used as clocks or strobes
except when gated with the Clock of the HC390A.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No 7A
Chip Complexity: 244 FETs or 61 Equivalent Gates
LOGIC DIAGRAM
1, 15
CLOCK A
÷2
COUNTER
3, 13 QA
CLOCK B 4, 12
÷5
COUNTER
5, 11
QB
6, 10
7, 9
QC
QD
2, 14
RESET
PIN 16 = VCC
PIN 8 = GND
This document contains information on a product under development. Motorola reserves the right
to change or discontinue this product without notice.
MC54/74HC390A
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
1
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
PIN ASSIGNMENT
CLOCK Aa
RESET a
QAa
CLOCK Ba
QBa
QCa
QDa
GND
1
2
3
4
5
6
7
8
16 VCC
15 CLOCK Ab
14 RESET b
13 QAb
12 CLOCK Bb
11 QBb
10 QCb
9 QDb
FUNCTION TABLE
Clock
AB
Reset Action
XX
X
X
H Reset
÷ 2 and ÷ 5
L Increment
÷2
L Increment
÷5
10/95
© Motorola, Inc. 1995
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