MB90F352CS Datasheet PDF - Fujitsu Media Devices

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MB90F352CS
Fujitsu Media Devices

Part Number MB90F352CS
Description 16-bit Proprietary Microcontroller
Page 20 Pages


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FUJITSU SEMICONDUCTOR
ADVANCE INFORMATION
XXXX-XXXXX-XE
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90350 Series
MB90F352/C(S), MB90V340(S)
s DESCRIPTION
The MB90350-series with one FULL-CAN interface (MB90V340: 2ch) and FLASH ROM is especially designed
for automotive and industrial applications. Its main feature is the on board CAN Interface, which conforms to V2.0
Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than
a normal full CAN approach. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip FLASH-ROM
program memory up to 128 Kbytes. An internal voltage booster removes the necessity for a second programming
voltage.
An on board voltage regulator provides 3 V to the internal MCU core. This creates a major advantage in terms
of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external 4
MHz clock.
The unit features an 4 channel Output Compare Unit and 6 channel Input Capture Unit with two separate 16-bit
free running timers. 2 UARTs (MB90V340: 3 UARTs) constitute additional functionality for communication pur-
poses.
s PACKAGES
64-pin Plastic LQFP
64-pin Plastic QFP
(FPT-64P-M09)
(FPT-64P-M06)
EMDC-WS 31/March/2003
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MB90350 Series
s FEATURES
• 16-bit core CPU; 4 MHz external clock (24 MHz internal, 42 ns instr. cycle time)
• New 0.35 µm CMOS Process Technology
• Internal voltage regulator supports 3 V MCU core, offering low EMI and low power consumption figures
• One FULL-CAN interface (MB90V340: 2ch); conforming to Version 2.0 Part A and Part B, flexible message
buffering (mailbox and FIFO buffering can be mixed)
• Powerful interrupt functions (8 progr. priority levels; 8 external interrupts)
• EI2OS - Automatic transfer function indep.of CPU; 16 ch. of intelligent I/O Services
• DMA
• 18-bit Time-base counter
• Watchdog Timer
• 2 full duplex UARTs (SCI/LIN) (MB90V340: 3 UARTs)
• One ch I2C with 400 kbit/s (devices with C-suffix)
• A/D Converter : 15 ch. analog inputs (Resolution 10 bits or 8 bit, conversion time 3µs)
• 16-bit reload timer ×4 ch
• ICU (Input capture) 16 bit x6 ch
• OCU (Output compare) 16 bit ×4 ch
• 16-bit free running timer ×2 ch (FRT0 : ICU 0/1, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)
• 8/16-bit Programmable Pulse Generator 6ch×16-bit / 10ch×8-bit (MB90V340: 8ch×16bit / 12ch×8bit)
• Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different
addressing modes; barrel shift; variety of pointers)
• 4-byte instruction execution queue
• signed multiply (16 bit×16 bit) and divide (32 bit/16 bit) instructions available
• Program Patch Function
• Fast Interrupt processing
• Low Power Consumption - 10 different power saving modes : (Sleep, Stop, CPU intermittent mode, ...)
• 32 kHz Subsytem Clock (devices without S-suffix)
• External bus interface
• Programmable input levels (Automotive / CMOS-Schmitt (initial level is Automotive), for external bus also TTL
level)
• Packages : 64-pin plastic QFP, 64-pin plastic LQFP
Controller Area Network (CAN) - License of Robert Bosch GmbH
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MB90350 Series
s PRODUCT LINEUP
Part Number
Parameter
MB90F352/C(S)
MB90V340(S)
CPU
F2MC-16LX CPU
System clock
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, x6, x8 ,1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz osc. PLL ×6)
ROM
Boot-block, Flash memory
128 Kbytes
External
RAM
4 Kbytes
30 Kbytes
Emulator-specific
power supply*1
Technology
None
0.35 µm CMOS with on-chip voltage regulator for internal 0.35 µm CMOS with on-chip
power supply + Flash memory with
voltage regulator for internal
On-chip charge pump for programming voltage
power supply
Operating
voltage range
3.5 - 5.5 V
(4.5 - 5.5 V if A/D Converter is used)
5 V ± 10%
Temperature range
40 °C to 105 °C
Package
QFP-64, LQFP-64
PGA-299
2 channels
3 channels
UART
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
I2C (400 kbit/s)
A/D
Converter
16-bit Reload Timer
(4 channels)
devices with ‘C’-suffix: 1 channel
devices without ‘C’-suffix:
2 channels
15 channels
15 channels
10-bit or 8-bit resolution
Conversion time : Min 3 µs include sample time (per one channel)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency)
Supports External Event Count function for 2 channels (Ch.1 and Ch.3)
16-bit
I/O Timer
(2 channels)
Signals an interrupt when overflowing
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = System clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1
I/O Timer 1 (clock input FRCK1) corresponds to
ICU 4/5/6/7, OCU 4/5/6/7
Both I/O Timers support Timer Clear when a match with
Output Compare (Channel 4)
I/O Timer 1 supports Timer
Clear when a match with Out-
put Compare (Channel 4)
16-bit
Output Compare
(4 channels)
Signals an interrupt when a match with 16-bit I/O Timer.
16-bit compare registers.
Four compare registers can be used to generate three PWM output signals.
16-bit
Input Capture
(6 channels)
Rising edge, falling edge or rising & falling edge sensitive
Signals an interrupt upon external event
(Continued)
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MB90350 Series
Part Number
Parameter
MB90F352/C(S)
MB90V340(S)
10 ch (8 bit) / 6 ch (16 bit)
12 8-bit reload counters
12 ch (8 bit) / 8 ch (16 bit)
16 8-bit reload counters
8/16-bit
Supports 8-bit and 16-bit operation modes
Programmable Pulse A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
Generator
8-bit prescaler plus 8-bit reload counter
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 102.4 µs@fosc = 5 MHz
(fsys = System clock frequency, fosc = Oscillation clock frequency)
1 channel
2 channels
CAN Interface
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps
External Interrupt
(8 channels)
Can be programmed edge sensitive or level sensitive
32 kHz Subclock for
low power operation
devices without ‘S’-suffix: yes
devices with ‘S’-suffix:
I/O Ports
Virtually all external pins can be used as general purpose I/O
All push-pull outputs
Bit-wise programmable as input/output or peripheral signal
Programmable in groups of 8 as CMOS schmitt trigger/ automotive inputs (default)
TTL input level programmable for external bus (default for external reset vector fetch)
Flash
Memory
Supports automatic programming, Embedded Algorith-
mTM*2
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Data retention time : 10 years
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
*1 : It is setting of Jumper switch SI when Emulation Pod (MB2147) is used.
Please refer to the Emulator hardware manual about details.
*2 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
4 EMDC-WS 31/March/2003 /usr/projects/mb90350/doc/datasheet/DS/MB90350_info_0.8.fm



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