M4A5-96 Datasheet PDF - Lattice Semiconductor

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M4A5-96
Lattice Semiconductor

Part Number M4A5-96
Description High Performance E2CMOS In-System Programmable Logic
Page 30 Pages


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ispMACH4A CPLD Family
High Performance E2CMOS®
In-System Programmable Logic
FEATURES
High-performance, E2CMOS 3.3-V & 5-V CPLD families
Flexible architecture for rapid logic designs
— Excellent First-Time-FitTM and ret feature
— SpeedLockingTM performance for guaranteed xed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
High speed
— 5.0ns tPD Commercial and 7.5ns tPD Industrial
— 182MHz fCNT
32 to 512 macrocells; 32 to 768 registers
44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Programmable pull-up or Bus-FriendlyTM inputs and I/Os
— Hot-socketing
— Programmable security bit
— Individual output slew rate control
Advanced E2CMOS process provides high-performance, cost-effective solutions
Lead-free package options
Lead-
Free
Package
Options
Available!
Publication# ISPM4A Rev: M
Amendment/0
Issue Date: September 2006



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3.3 V Devices
Feature
Macrocells
User I/O options
tPD (ns)
fCNT (MHz)
tCOS (ns)
tSS (ns)
Static Power (mA)
JTAG Compliant
PCI Compliant
M4A3-32
32
32
5.0
182
4.0
3.0
20
Yes
Yes
Table 1. ispMACH 4A Device Features
M4A3-64
64
32/64
5.5
167
4.0
3.5
25/52
Yes
Yes
M4A3-96
96
48
5.5
167
4.0
3.5
40
Yes
Yes
M4A3-128
128
64
5.5
167
4.0
3.5
55
Yes
Yes
M4A3-192
192
96
6.0
160
4.5
3.5
85
Yes
Yes
M4A3-256
256
128/160/192
5.5
167
4.0
3.5
110/150
Yes
Yes
M4A3-384
384
160/192
6.5
154
4.5
3.5
149/155
Yes
Yes
M4A3-512
512
160/192/256
7.5
125
5.5
5.0
179
Yes
Yes
5 V Devices
Feature
Macrocells
User I/O options
tPD (ns)
fCNT (MHz)
tCOS (ns)
tSS (ns)
Static Power (mA)
JTAG Compliant
PCI Compliant
M4A5-32
32
32
5.0
182
4.0
3.0
20
Yes
Yes
M4A5-64
64
32
5.5
167
4.0
3.5
25
Yes
Yes
M4A5-96
96
48
5.5
167
4.0
3.5
40
Yes
Yes
M4A5-128
128
64
5.5
167
4.0
3.5
55
Yes
Yes
M4A5-192
192
96
6.0
160
4.5
3.5
74
Yes
Yes
M4A5-256
256
128
6.5
154
5.0
3.5
110
Yes
Yes
2 ispMACH 4A Family



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GENERAL DESCRIPTION
The ispMACH4A family from Lattice offers an exceptionally flexible architecture and delivers a superior
Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools.
The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market,
greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512
macrocells with 100% utilization and 100% pin-out retention. The ispMACH 4A families offer 5-V (M4A5-
xxx) and 3.3-V (M4A3-xxx) operation.
ispMACH 4A products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1)
interface. JTAG boundary scan testing also allows product testability on automated test equipment for
device connectivity.
All ispMACH 4A family members deliver First-Time-Fit and easy system integration with pin-out retention
after any design change and refit. For both 3.3-V and 5-V operation, ispMACH 4A products can deliver
guaranteed fixed timing as fast as 5.0 ns tPD and 182 MHz fCNT through the SpeedLocking feature when
using up to 20 product terms per output (Table 2).
Device
M4A3-32
M4A5-32
M4A3-64/32
M4A5-64/32
M4A3-64/64
M4A3-96
M4A5-96
M4A3-128
M4A5-128
M4A3-192
M4A5-192
M4A3-256/128
M4A5-256/128
M4A3-256/192
M4A3-256/160
M4A3-384
M4A3-512
-5
C
Table 2. ispMACH 4A Speed Grades
Speed Grade
-55 -6 -65 -7 -10 -12 -14
C, I C, I
I
C
C, I C, I
I
C
C, I C, I
I
C
C, I C, I
I
C
C, I C, I
I
C
C, I C, I
I
C C C, I C, I I
C C C, I I
C C, I I
C
C, I C, I
I
C C, I C, I I
Note:
1. C = Commercial, I = Industrial
ispMACH 4A Family
3



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The ispMACH 4A family offers 20 density-I/O combinations in Thin Quad Flat Pack (TQFP), Plastic
Quad Flat Pack (PQFP), Plastic Leaded Chip Carrier (PLCC), Ball Grid Array (BGA), fine-pitch BGA
(fpBGA), and chip-array BGA (caBGA) packages ranging from 44 to 388 pins (Table 3). It also offers I/O
safety features for mixed-voltage designs so that the 3.3-V devices can accept 5-V inputs, and 5-V devices
do not overdrive 3.3-V inputs. Additional features include Bus-Friendly inputs and I/Os, a programmable
power-down mode for extra power savings and individual output slew rate control for the highest speed
transition or for the lowest noise transition.
Table 3. ispMACH 4A Package and I/O Options (Number of I/Os and dedicated inputs in Table)
3.3 V Devices
Package
M4A3-32 M4A3-64 M4A3-96 M4A3-128 M4A3-192 M4A3-256 M4A3-384 M4A3-512
44-pin PLCC
32+2 32+2
44-pin TQFP
32+2 32+2
48-pin TQFP
32+2 32+2
100-pin TQFP
64+6 48+8 64+6
100-pin PQFP
64+6
100-ball caBGA
64+6
144-pin TQFP
96+16
144-ball fpBGA
96+16
208-pin PQFP
128+14, 160
160
160
256-ball fpBGA
128+14, 192
192
192
256-ball BGA
128+14
192
388-ball fpBGA
256
Package
44-pin PLCC
44-pin TQFP
48-pin TQFP
100-pin TQFP
100-pin PQFP
144-pin TQFP
208-pin PQFP
M4A5-32
32+2
32+2
32+2
M4A5-64
32+2
32+2
32+2
5 V Devices
M4A5-96
48+8
M4A5-128 M4A5-192 M4A5-256
64+6
64+6
96+16
128+14
4 ispMACH 4A Family



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