LTC6801 Datasheet PDF - Linear Technology

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LTC6801
Linear Technology

Part Number LTC6801
Description Independent Multicell Battery Stack Fault Monitor
Page 28 Pages


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Electrical Specifications Subject to Change
LTC6801
FEATURES
n Monitors Up to 12 Li-Ion Cells in Series (60V Max)
n Stackable Architecture Enables >1000V Systems
n Adjustable Overvoltage and Undervoltage
Detection
n Self Test Features Guarantee Accuracy
n Robust Fault Detection Using Differential Signals
n Simple Pin-Strapped Configuration Allows Battery
Monitoring without a Microcontroller
n 15ms to Monitor All Cells in a System
n Programmable Response Time
n Two Temperature Monitor Inputs
n Low Power Idle Mode
n 36-Lead SSOP Package
APPLICATIONS
n Redundant Battery Monitor
n Hybrid Electric Vehicles
n Battery Backup Systems
n Power Systems Using Multiple Battery Cells
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
www.DataSheet4U.com
Independent Multicell
Battery Stack Fault Monitor
DESCRIPTION
The LTC®6801 is a multicell battery monitoring IC incor-
porating a 12-bit ADC, a precision independent voltage
reference, sampled comparator, and a high voltage input
multiplexer. The LTC6801 can monitor as many as 12 series
connected battery cells for overvoltage, undervoltage, and
overtemperature conditions, indicating whether the cells
are within specified parameters. The LTC6801 generates
a clock output when no fault conditions exist. Differential
clocking provides high noise immunity and ensures that
battery stack fault conditions cannot be hidden by frozen
bits or short circuit conditions.
Each LTC6801 can operate with a battery stack voltage up
to 60V and multiple LTC6801 devices can be stacked to
monitor each individual cell in a long battery string. When
multiple devices are stacked, the status signal of each
LTC6801 can be daisy-chained, without opto-couplers or
isolators, providing a single status output for the entire
battery string.
The LTC6801 is configurable by external pin strapping.
Adjustable overvoltage and undervoltage thresholds sup-
port various Li-Ion chemistries. Selectable measurement
times allow users to save power.
BLOCK DIAGRAM
NEXT HIGHER
CELL PACK
1 V+
C12
2
3 C11
12 C2
C1
13
V–
14
MUX
LTC6801
CONTROL
12 LOGIC
ADC
ENABLE ISOLATION
INPUT
“CELLS GOOD”
20
CLOCK SIGNAL
INPUT ENABLES
THE LTC6801
NEXT LOWER
CELL PACK
VTEMP1 VTEMP2
15 16
NTC
VREF
17
REFERENCE
NTC
22
STATUS
OUTPUT
6801 TA01a
CLOCK SIGNAL
OUTPUT INDICATES
SYSTEM “OK”
0V Detection Level Error
1.0 V+ = 43.2V
0.8 OV = 4.120V
0.6
5 TYPICAL UNITS
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
6801 TA01b
6801p
1



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LTC6801
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Total Supply Voltage (V+ to V) .................................60V
Input Voltage (Relative to V)
C1 ............................................................ –0.3V to 9V
C12 ...........................................V+ –0.3V to V+ + 0.3V
All Other Pins (Not C Inputs) ................... –0.3V to 7V
Voltage Between Inputs
Cn to Cn-1* ............................................. –0.3V to 9V
C12 to C8............................................... –0.3V to 25V
C8 to C4................................................. –0.3V to 25V
C4 to V................................................. –0.3V to 25V
Operating Temperature Range.................. –40°C to 85°C
Specified Temperature Range .................. –40°C to 85°C
Junction Temperature ........................................... 150°C
Storage Temperature Range................... –65°C to 150°C
*n = 2 to 12
PIN CONFIGURATION
V+ 1
C12 2
C11 3
C10 4
C9 5
C8 6
C7 7
C6 8
C5 9
C4 10
C3 11
C2 12
C1 13
V14
VTEMP1 15
VTEMP2 16
VREF 17
VREG 18
TOP VIEW
36 OV1
35 OV0
34 UV1
33 UV0
32 HYST
31 CC1
30 CC0
29 SLT
28 SLTOK
27 DC
26 EOUT
25 EOUT
24 SIN
23 SIN
22 SOUT
21 SOUT
20 EIN
19 EIN
G PACKAGE
36-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 70°C/W
ORDER INFORMATION
wwwL.DEAaDtaSFRheEEetF4IUN.IcSoHm TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
LTC6801IG#PBF
LTC6801IG#TRPBF LTC6801IG
36-Lead Plastic SSOP
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
SPECIFIED TEMPERATURE RANGE
–40°C to 85°C
6801p
2



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LTC6801
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, V+ = 43.2V, V= 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX
UNITS
DC Specifications
VERR
VCELL
VCM
Measurement Error
Cell Voltage Range
Common Mode Voltage Range Measured
Relative to V
VCELL
VCELL
VCELL
VCELL
>
>
0.8V,
0.8V,
0.8V,
0.8V,
10V
10V
10V
10V
<
<
<
<
V+
V+
V+
V+
<
<
<
<
50V
50V
50V
50V
Full Scale Voltage Range
VERR Specifications Met
Range of Inputs Cn, n = 3 to 11
Range of Input C2
Range of Input C1
–0.5
l –1
–1.5
l –2
5
0.5
1
1.5
2
l 1.8
l 1.2
l0
5•n
10
5
%
%
%
%
V
V
V
V
VOV Overvoltage (OV) Detection Level
Programmed for
10V < V+ < 50V
4.128V,
Increasing
VCELL,
l
4.079
4.120
4.161
V
VUV
Undervoltage (UV) Detection Level
Programmed for
10V < V+ < 50V
2.112V,
Decreasing
VCELL,
l
2.087
2.108
2.129
V
VTV Temperature Input Detection Level Error 10V < V+ < 50V
(Relative to VREF/2)
HYS UV/OV Detection Hysteresis Error
10V < V+ < 50V
(Relative to Selected Value)
l –18
l –25
12 mV
25 %
VREF Reference Pin Voltage
VREF Pin Loaded With 100k to V
3.043 3.058 3.073
l 3.038 3.058 3.078
V
V
Reference Voltage Temperature Coefficient
5 ppm/˚C
Reference Voltage Hysteresis
Reference Voltage Long Term Drift
50 ppm
60 ppm/√khr
VREG Regulator Pin Voltage
Regulator Pin Short Circuit Current Limit
VS Supply Voltage, V+ Relative to V
IB Input Bias Current
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IM Supply Current, Monitor Mode
10 < VS < 50, No Load
10 < VS < 50, ILOAD = 4mA
VERR Specifications Met
In/Out of Pins C1 Thru C12
When Measuring Cells During Self Test
When Measuring Cells
When Idle
Current Into the V+ Pin While Monitoring
for UV and OV Conditions, FENA = 10kHz
Continuous Monitoring
Monitor Every 130ms
Monitor Every 500ms
l
l
l
l
l
l
4.5
4.1
5
10
–10
500
5 5.5
4.8
9
50
100
10
1
700 1000
200
90
V
V
mA
V
μA
μA
nA
μA
μA
μA
IQS Supply Current, Idle
LTC6801 Timing Specifications
Current into the V+ Pin When Idle, FENA = 0 l 20 30 40
μA
TCYCLE
Measurement Cycle Time
DC = CC1 = CC0 = VREG
FENA Valid EIN/EIN Frequency
TENA Valid EIN/EIN Period = 1/ FENA
DCENA
Valid EIN/EIN Duty Cycle
FENA = 50kHz
LTC6801 Single Ended Digital I/O Specifications (SLT, SLTOK Pins)
VIH Digital Input Voltage High
SLT Pin
VIL Digital Input Voltage Low
SLT Pin
VODL
Digital Output Voltage Low, Open Drain
SLT Pin, 10k to VREG
VOH Digital Output Voltage High
SLTOK Pin, 10k to V
VOL Digital Output Voltage Low
SLTOK Pin, 10k to VREG
l 13.5 15.5 17.5
l2
50
l 20
500
l 40
60
l2
l
l
l VREG – 0.3
l
0.5
0.3
0.3
ms
kHz
μs
%
V
V
V
V
V
6801p
3



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LTC6801
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, V+ = 43.2V, V= 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX
IPU-ST
Pull-Up Current
SLT Pin
LTC6801 Differential Digital Input Specifications (SIN/SIN, EIN/EIN Pins) (See Figure 1)
l 2.5 5 10
UNITS
μA
VIDH
VIDL
Minimum Differential Input Voltage High
Minimum Differential Input Voltage Low
Differential Voltage Applied Between SIN
and SIN or EIN and EIN
l
l
1.7
VIL Valid Input Voltage Low
Low Side of Differential Signal, Ref. to Vl
0
VIH Valid Input Voltage High
High Side of Differential Signal, Ref. to Vl 2.5
VDHYS
Differential Input Hysteresis
VOPEN
Open Circuit Voltage
l2
RINCM
Input Resistance, Common Mode
RINDIFF
Input Resistance, Differential
Between SIN to SIN, EIN to EIN
LTC6801 Differential Digital Output Specifications (SOUT/SOUT, EOUT/EOUT Pins)
l 100
l 200
VODH
Digital Output Voltage High
Output Pins Loaded With 100k to V
l VREG – 0.3
VODL Digital Output Voltage Low
Output Pins Loaded With 100k to VREG
l
LTC6801 Three-Level Digital Input Specifications (OV0, OV1, UV0, UV1, HYST, DC, CC0 and CC1 Pins)
1
2.5
150
300
–1.7
1.2
6
3
0.3
V
V
V
V
V
V
V
V
V3IH Three-Level Digital Input Voltage High
V3IM Three-Level Digital Input Voltage Mid
V3IL Three-Level Digital Input Voltage Low
IPU Pull-Up Current
Pins DC, CC0, CC1, UV0 and UV1
IPD Pull-Down Current
Pins HYST, OV0 and OV1
l VREG – 0.3
l VREF – 0.3
l
VREF + 0.3
0.3
l 0.5
1
2
l 0.5
1
2
V
V
V
μA
μA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
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EIN
MAX, VIH
VIDH
(VALID HIGH WHEN
EIN – EIN ≥ VIDH)
TENA
MIN, VIH
MAX, VIL
V– = 0V
EIN
(VALID
LOW
VIDL
WHEN EIN
EIN
VIDL)
Figure 1. Differential Input Specifications
6801 F01
6801p
4



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