LT5524 Datasheet PDF - Linear Technology

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LT5524
Linear Technology

Part Number LT5524
Description Low Distortion IF Amplifier/ADC Driver
Page 16 Pages


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FEATURES
Output IP3 at 100MHz: 40dBm
Maximum Output Power: 16dBm
Bandwidth: LF to 540MHz
Propagation Delay: 0.8ns
Maximum Gain: 27dB
Gain Control Range: 22.5dB
Gain Control Step: 1.5dB
Gain Control Settling Time: 500ns
Noise Figure: 8.6dB at 100MHz (Max Gain)
Output Noise Floor: –138dBm/Hz (Max Gain)
Reverse Isolation: –92dB
Single Supply: 4.75V to 5.25V
Shutdown Mode
Enable/Disable Time: 1µs
Differential I/O Interface
20-Lead TSSOP Package
U
APPLICATIO S
High Linearity ADC Driver
IF Sampling Receivers
VGA IF Power Amplifier
50Driver
Instrumentation Applications
LT5524www.DataSheet4U.com
Low Distortion IF
Amplifier/ADC Driver with
Digitally Controlled Gain
DESCRIPTIO
The LT®5524 is a programmable gain amplifier (PGA) with
bandwidth extending from low frequency (LF) to 540MHz.
It consists of a digitally controlled variable attenuator,
followed by a high linearity amplifier. Four parallel digital
inputs control the gain over a 22.5dB range with 1.5dB
step resolution. An on-chip power supply regulator/filter
helps isolate the amplifier signal path from external noise
sources.
The LT5524’s open-loop architecture offers stable opera-
tion for any practical load conditions, including peaking-
free AC response when driving capacitive loads, and
excellent reverse isolation.
The LT5524 may be operated broadband, where the out-
put differential RC time constant sets the bandwidth, or it
may be used as a narrowband driver with the appropriate
output filter.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Patents Pending.
TYPICAL APPLICATIO
0.1µF
CHOKE
5V
CHOKE
0.1µF
RF
INPUT
IF IF
BPF AMP
LT5524
100
LO 0.1µF
0.1µF
GAIN CONTROL
4 LINES
ADC
5524 TA01
Output IP3 vs Frequency, ROUT = 200
54
51
48
45
MAX GAIN
42
39
1.5dB
36 ATTENUATION
STEP
33
30
0
50 100 150
FREQUENCY (MHz)
200
5524 TA02
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ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Power Supply Voltage (VCC1, VCC2) .......................... 6V
Output DC Voltage (OUT+, OUT) ............................. 7V
Control Input Voltage (EN, PGAx) ............. –0.5V to VCC
Signal Input Voltage (IN+, IN) ................... –0.5V to 3V
Operating Ambient Temperature Range .. – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
PACKAGE/ORDER INFORMATION
EN 1
VCC1 2
GND 3
GND 4
IN+ 5
IN6
GND 7
GND 8
PGA0 9
PGA1 10
TOP VIEW
21
20 NC
19 VCC2
18 GND
17 GND
16 OUT
15 OUT+
14 GND
13 GND
12 PGA3
11 PGA2
ORDER PART
NUMBER
LT5524EFE
FE PACKAGE
20-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 38°C/W
EXPOSED PAD (PIN 21) IS GND
MUST BE SOLDERED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
PROGRA ABLE GAI SETTI GS
ATTENUATION STEP
RELATIVE TO MAX GAIN
1 0dB
2 –1.5dB
3 –3.0dB
4 –4.5dB
5 –6.0dB
6 –7.5dB
7 –9.0dB
8 –10.5dB
9 –12.0dB
10 –13.5dB
11 –15.0dB
12 –16.5dB
13 –18.0dB
14 –19.5dB
15 –21.0dB
16 –22.5dB
*ROUT = 200
PGA0
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
PGA1
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
PGA2
High
High
High
High
Low
Low
Low
Low
High
High
High
High
Low
Low
Low
Low
PGA3
High
High
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
Low
Low
POWER GAIN*
27.0dB
25.5dB
24.0dB
22.5dB
21.0dB
19.5dB
18.0dB
16.5dB
15.0dB
13.5dB
12.0dB
10.5dB
9.0dB
7.5dB
6.0dB
4.5dB (Note 3)
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DC ELECTRICAL CHARACTERISTICS VCC = 5V, VCCO = 5V, EN = 3V, TA = 25°C, unless otherwise noted.
(Note 7) (Test circuits shown in Figures 9 and 10)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
Normal Operating Conditions
VCC Supply Voltage (Pins 2, 19)
(Note 4)
4.75 5 5.25
VCCO OUT+, OUTOutput Pin DC Common Mode Voltage OUT+, OUTConnected to VOSUP via
3
Choke Inductors or Resistors (Note 5)
5 5.5
V
V
Shutdown DC Characteristics, EN = 0.6V
VIN(BIAS) IN+, INBias Voltage
IIL(PGA)
PGAO, PGA1, PGA2, PGA3 Input Current
IIH(PGA)
IOUT
PGAO, PGA1, PGA2, PGA3 Input Current
OUT+, OUTCurrent
ICC VCC Supply Current
Enable and PGA Inputs DC Characteristics
Max Gain (Note 6)
VIN = 0.6V
VIN = 5V
All Gain Settings
All Gain Settings (Note 4)
1.15 1.3 1.5
20
20
20
44 100
V
µA
µA
µA
µA
VIL
VIH
IIL(PGA)
IIH(PGA)
IIL(EN)
IIH(EN)
EN and PGAx Input Low Voltage
EN and PGAx Input High Voltage
PGAO, PGA1, PGA2, PGA3 Input Current
PGAO, PGA1, PGA2, PGA3 Input Current
EN Input Current
EN Input Current
DC Characteristics, EN = 3V
VIN(BIAS) IN+, INBias Voltage
RIN Input Differential Resistance
gm Amplifier Transconductance
IOUT OUT+, OUTQuiescent Current
IOUT(OFFSET) Output Current Mismatch
ICC VCC1 + VCC2 Supply Current
x = 0, 1, 2, 3
x = 0, 1, 2, 3
VIN = 0.6V
VIN = 3V and 5V
VIN = 0.6V
VIN = 3V
VIN = 5V
Max Gain (Note 6)
All Gain Settings (DC)
Max Gain
All Gain Settings, VOUT = 5V
All Gain Settings, IN+, INOpen
Max Gain (Note 4)
Min Gain (Note 4)
0.6 V
3V
20 µA
15 30
µA
4 20 µA
18
38 100
µA
µA
1.34 1.48 1.65
V
122
0.15 S
17 20 24 mA
100 µA
34 40 mA
36 43 mA
ICC(TOTAL) Total Supply Current
ICC + 2 • IOUT (Max Gain)
75 91 mA
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AC ELECTRICAL CHARACTERISTICS VCC = 5V, VCCO = 5V, EN = 3V, TA = 25°C, ROUT = 200. Maximum gain
specifications are with respect to differential inputs and differential outputs, unless otherwise noted.
(Note 7) (Test circuits shown in Figures 9 and 10)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
Dynamic Performance
BW Large-Signal –3dB Bandwidth
VOUT(CLIP) Output Voltage Clipping Levels
POUT(MAX) Clipping Limited Maximum Sinusoidal
Output Power
gm Amplifier Transconductance
S12 Reverse Isolation
Distortion and Noise
All Gain Settings (Note 8), ROUT = 100
Each OUT+, OUTwith Respect to Ground
(Note 11)
All Gain Settings, Single Tone,
fIN = 100MHz (Note 10)
Max Gain, fIN = 100MHz
fIN = 100MHz (Note 9)
LF to 540
28
16
0.15
– 92
MHz
V
dBm
S
dB
OIP3
HD2
HD3
NFLOOR
NF
Output Third Order Intercept Point for
PGA0 = High (PGA1, PGA2, PGA3 Any State)
Output Third Order Intercept Point for
PGA0 = Low (PGA1, PGA2, PGA3 Any State)
Second Harmonic Distortion
Third Harmonic Distortion
Output Noise Floor
(PGAO, PGA2, PGA3 Any State)
Noise Figure
PGA Settling Time
Enable/Disable Time
POUT = 4dBm (Each Tone), 200kHz Tone Spacing,
fIN = 100MHz
POUT = 4dBm (Each Tone), 200kHz Tone Spacing,
fIN = 100MHz
POUT = 5dBm (Single Tone), fIN = 50MHz
POUT = 5dBm (Single Tone), fIN = 50MHz
PGA1 = High, fIN = 100MHz
PGA1 = Low, fIN = 100MHz
Max Gain Setting, fIN = 100MHz
Output Settles within 10% of Final Value
Output Settles within 10% of Final Value
+40
+36
– 76
–72
–138
–140
8.6
500
600
dBm
dBm
dBc
dBc
dBm/Hz
dBm/Hz
dB
ns
ns
Amplifier Power Gain and Gain Step
GMAX
Maximum Gain
fIN = 20MHz and 200MHz
GMIN
Minimum Gain
fIN = 20MHz and 200MHz
GSTEP
Gain Step Size
fIN = 20MHz and 200MHz
Gain Step Accuracy
fIN = 20MHz and 200MHz
Amplifier I/O Impedance (Parallel Values, Specified Differentially)
RIN Input Resistance
CIN Input Capacitance
RO Output Resistance
CO Output Capacitance
fIN = 100MHz
fIN = 100MHz
fIN = 100MHz
fIN = 100MHz
27
4.5
0.8 1.5 2.2
±0.2
122
2
5
1.7
dB
dB
dB
dB
pF
k
pF
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: All voltage values are with respect to ground.
Note 3: Default state for open PGA inputs.
Note 4: VCC1 and VCC2 (Pins 2 and 19) are internally connected.
Note 5: External VOSUP is adjusted such that VCCO output pin common
mode voltage is as specified when resistors are used. For choke inductors
or transformer, VOSUP = VCCO = 5V typ.
Note 6: Internally generated common mode input bias voltage requires
capacitive or transformer coupling to the signal source.
Note 7: Specifications over the –40°C to 85°C operating temperature
range are assured by design, characterization and correlation with
statistical process controls. Gain always refers to power gain. Input
matching is assumed. PIN is the available input power. POUT is the power
into the external load, ROUT, as seen by the LT5524 differential outputs. All
dBm figures are with respect to 50.
Note 8: High frequency operation is limited by the RC time constants at
the input and output ports. The low frequency (LF) roll-off is set by I/O
interface choice.
Note 9: Limited by package and board isolation.
Note 10: See “Clipping Free Operation” in the Applications Information
section. Refer to Figure 7.
Note 11: Although the instantaneous AC voltage on the OUT+ or OUTpins
may in some situations safely exceed 8V (with respect to ground), in no
case should the DC voltage on these pins be allowed to exceed the
ABSMAX tested limit of 7V.
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