U® L LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
BRUSHLESS DC MOTOR COMMUTATOR/CONTROLLER
• Direct drive of P-Channel and N-Channel FETs (LS7260)
• Direct drive of PNP and NPN transistors (LS7262)
CONNECTION DIAGRAM - TOP VIEW
• Six outputs drive power switching bridge directly
• Open or closed loop motor speed control.
• +5V to +28V operation (Vss - VDD).
OUT 1 2
• Externally selectable input to output code for 60°,
OUT 2 3
18 V DD (-V)
120°, 240°, or 300° electrical sensor spacing.
• Three or four phase operation
• Analog Speed control
• Direction control
OUT 3 4
OUT 4 6
• Output Enable control
OUT 5 7
• Positive Static Braking
OUT 6 8
13 V TRIP
• Overcurrent Sensing
• LS7260, LS7262 (DIP); LS7260-S, LS7262-S (SOIC)
LS7260-TS, LS7262-TS (TSSOP) - See Connection Diag.
12 O V E R C U R R E N T S E N S E
11 V SS (+V)
The LS7260/LS7262 are monolithic, MOS integrated cir-
cuits designed to generate the signals necessary to con-
trol a three phase or four phase brushless DC motor.
They are the basic building blocks of a brushless DC
motor controller. The circuits respond to changes at the
SENSE inputs, originating at the motor position sensors,
to provide electronic commutation of the motor wind-
ings. Pulse Width Modulation of outputs for motor speed
control is accomplished through either the ENABLE in-
put or through the Analog input (VTRIP) in conjunction
with the OSCILLATOR input. Overcurrent circuitry is
provided to protect the windings, associated drivers and
power supply. The overcurrent circuitry causes the ex-
ternal output drivers to switch off immediately upon
sensing the overcurrent condition and on again only
when the overcurrent condition disappears and the pos-
itive edge of either the ENABLE input or the sawtooth
OSCILLATOR occurs. This limits the overcurrent sense
cycling to the chopping rate of the ENABLE input or the
A positive braking feature is provided to effect rapid de-
celeration. While the LS7262 is designed for driving
NPN and PNP transistors (See Fig. 2), the LS7260 is
designed to drive both NMOS and PMOS Power FETs
and develops a full 12V drive for both the N-Channel
and P-Channel devices (See Fig. 1) when using a 12V
COMMUTATION SELECTS (Pins 1, 20)
These inputs are used to select the proper sequence of outputs
based on the electrical separation of the motor position sensors.
See Table 3. Note that in all cases the external output drivers
are disabled for invalid SENSE input codes. Internal pull down
resistors are provided at Pins 1 and 20 causing a logic zero
when these pins are left open.
FORWARD/REVERSE (Pin 19)
This input is used to select the proper sequence of Outputs for
the desired direction of rotation for the Motor (See Table 3). An
internal pull-up resistor holds the input high when left open.
SENSE INPUTS (Pins 15, 16, 17)
These inputs provide control of the output commutation
sequence as shown in Table 3. S1, S2, S3 originate in the posi-
tion sensors of the motor and must sequence in cycle code or-
der. Hall Switch pull-up resistors are provided at Pins 15, 16 and
17. The positive supply of the Hall devices should be common
to the chip Vss.
BRAKE (Pin 9)
For the LS7262, a high level at this input unconditionally turns
OFF Outputs 1, 2 and 3 and turns ON Outputs 4, 5 and 6 (See
Fig. 2). For the LS7260, a high level at this input turns ON Out-
puts 1, 2 and 3 and Outputs 4, 5 and 6 (See Fig. 1). In both
cases, transistors Q101, Q102 and Q103 cut off and transistors
Q104, Q105 and Q106 turn on, shorting the windings together,
The BRAKE has priority over all other inputs.