TRIGGER Input (TRIG, Pin 18)
TIMER RESET Input (RESET, Pin 7)
A transition at the TRIG input causes OUT to switch with or When RESET input switches high, any timeout in progress
without delay, depending on the selected mode. The TRIG in- is aborted and OUT switches high without delay. With RE-
put to OUT transition relation is always opposite in polarity, SET high, OUT remains high. When RESET switches low
with the exception of One-Shot mode. (See Mode definitions with TRIG low in any mode, OUT remains high. When RE-
above.) TRIG input has an internal pull-down resistor of SET switches low with TRIG high in Delayed Operate and
about 500k Ω and is buffered by a Schmitt trigger to provide Dual Delay modes, the delay timer is started and OUT
switches low at the end of the delay timeout. When RE-
SET switches low with TRIG high in Delayed Release
LS7211N TIME BASE Input (RC/CLOCK, Pin 4)
mode, OUT switches low without delay. When RESET
For LS7211N, the basic timing signal is applied at the RC/ switches low with TRIG high in One-Shot mode, OUT re-
CLOCK input. The clock can be provided from either an ex- mains high. RESET input has an internal pull-down resistor
ternal source or generated by an internal oscillator by con- of about 500kΩ, and is buffered by a Schmitt Trigger to
necting an R-C network to this input.
provide input hysteresis.
The frequency of oscillation is given by ƒ 1/RC. Chip-to-
chip oscillation tolerance is ± 5% for a fixed value of RC.
The minimum resistance, R MIN = 4000Ω, VDD = + 4V
VSS (-V, Pin 8)
Supply voltage negative terminal or GND.
= 1200Ω, VDD = +10V
= 600Ω, VDD = +18V
DELAY Output (OUT, Pin 9)
Except in One-Shot mode, OUT switches with or without
The external clock mode is selected by applying a logic low delay (depending on mode) in inverse relation to the logic
to the RCS/CLKS input (Pin 5); the internal oscillator mode is level of the TRIG input. In One-Shot mode, a timed low
selected by applying a high level to the RCS/CLKS input.
level is produced at OUT, in response to a positive transi-
tion of the TRIG input.
LS7212N TIME BASE Input (XTLI/CLOCK, Pin 4)
For LS7212N, the basic timing clock is applied to the XLTI/ WEIGHTING BIT Inputs (WB7 to WB0, Pins 10 - 17)
CLOCK input from either an external clock source or gener- Inputs WB0 through WB7 are binary weighted delay bits
ated by an internal crystal oscillator by connecting a crystal used to program the delay according to the following
between XTLI/CLOCK input and the XTLO output (Pin 5).
LS7211N TIME BASE SELECT Input (RCS/CLKS, Pin 5) One-Shot Mode: Pulse width = SW
For LS7211N, the external clock operation at Pin 4 is se-
lected by applying a logic low to the RCS/CLKS input. The in-
ternal oscillator option with RC timer at Pin 4 is selected by All other Modes: Delay = SW + 0.5
applying a logic high at the RCS/CLKS input. RCS/CLKS in-
put has an internal pull-down resistor of about 500kΩ.
S = Prescale factor (See Table 2)
LS7212N TIME BASE Output (XTLO, Pin 5)
ƒ = Time base frequency at Pin 4
For LS7212N, when a crystal is used for generating the time W = WB0 + WB1 + ....... WB7
base oscillation, the crystal is connected between XTLI/
CLOCK and XTLO pins.
The weighting factor W is calculated by substituting in the
equation above for W, the weighted values for all the WB
PRESCALER SELECT Input (PSCLS, Pin 6)
inputs that are at logic high. The weighted values for the
The PSCLS input is a 3-state input, which selects one of WB inputs are shown in Table 3. Each WB input has an in-
three prescale factors according to Table 2.
ternal pull-down resistor of about 500kΩ.
TABLE 2. PRESCALE FACTOR SELECTION
TABLE 3. BIT WEIGHTS
S (Prescale Factor )
Using prescale factors of 3000 and 3600, delays in units of
minutes can be produced from 50Hz and 60Hz line sources.
Prescale factors of 32,768 and 32,768 x 60 can be used to
generate accurate delays in units of seconds and minutes,
respectively, from a 32kHz watch crystal.
VDD (+V, Pin 3)
Supply voltage positive terminal.