LS7212N Datasheet PDF - LSI

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LS7212N
LSI

Part Number LS7212N
Description PROGRAMMABLE DIGITAL DELAY TIMER
Page 8 Pages


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LSI/CSI
LS7211N-7212N
U® L LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
A3800
PROGRAMMABLE DIGITAL DELAY TIMER
July 2009
FEATURES:
• 8-bit programmable delay from microseconds to days
• On chip oscillator (RC or Crystal) or external clock time base
• Selectable prescaler for real time delay generation based
on 50Hz/60Hz time base or 32,768Hz watch crystal
• Four operating modes
• Reset input for delay abort
• Low quiescent and operating current
• Direct relay drive
• +3V to +18V operation (VDD - VSS)
LS7211N, LS7212N (DIP); LS7211N-S, LS7212N-S (SOIC)
- See Figure 1 -
DESCRIPTION:
The LS7211N and LS7212N are CMOS integrated circuits for
generating digitally programmable delays. The delay is con-
trolled by 8 binary weighted inputs, WB0 - WB7, in conjunction
with an applied clock or oscillator frequency. The programmed
time delay manifests itself in the Delay Output (OUT) as a func-
tion of the Operating Mode selected by the Mode Select inputs
A and B: One-Shot, Delayed Operate, Delayed Release or Dual
Delay. The time delay is initiated by a transition of the Trigger
Input (TRIG).
PIN ASSIGNMENT - TOP VIEW
A1
B
V DD (+V)
2
3
RC/CLOCK 4
RCS/CLKS
PSCLS
5
6
RESET 7
V SS (-V)
OUT
8
9
18 TRIG
17 WB0
16 WB1
15 WB2
14 WB3
13 WB4
12 WB5
11 WB6
10 WB7
A1
B2
18 TRIG
17 WB0
I/O DESCRIPTION:
MODE SELECT Inputs A & B (Pins 1 & 2)
The 4 operating modes are selected by Inputs A and B
according to Table 1
V DD (+V) 3
XTLI/CLOCK
XTLO
4
5
16 WB1
15 WB2
14 WB3
TABLE 1. MODE SELECTION
A B MODE
0 0 One-Shot (OS)
0 1 Delayed Operate (DO)
1 0 Delayed Release (DR)
1 1 Dual Delay (DD)
PSCLS 6
RESET 7
V SS (-V) 8
OUT 9
FIGURE 1
13 WB4
12 WB5
11 WB6
10 WB7
Each input has an internal pull-up resistor of about 500k.
One-Shot Mode (OS)
A positive transition at the TRIG input causes OUT to switch
low without delay and starts the delay timer. At the end of the
programmed delay timeout, OUT switches high. If a delay time-
out is in progress when a positive transition occurs at the TRIG
input, the delay timer will be restarted. A negative transition at
the TRIG input has no effect.
Delayed Operate Mode (DO)
A positive transition at the TRIG input starts the delay timer. At
the end of the delay timeout, OUT switches low. A negative
transition at the TRIG input causes OUT to switch high without
delay. OUT is high when TRIG is low.
7211N-07209-1
Delayed Release Mode (DR)
A negative transition at the TRIG input starts the delay tim-
er. At the end of the delay timeout, OUT switches high. A
postive transition at the TRIG input causes OUT to switch
low without delay. OUT is low when TRIG is high.
Dual Delay Mode (DD)
A positive or negative transition at the TRIG input starts
the delay timer. At the end of the delay timeout, OUT
switches to the logic state which is the inverse of the TRIG
input. If a delay timeout is in progress when a transition
occurs at the TRIG input, the delay timer is restarted.



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TRIGGER Input (TRIG, Pin 18)
TIMER RESET Input (RESET, Pin 7)
A transition at the TRIG input causes OUT to switch with or When RESET input switches high, any timeout in progress
without delay, depending on the selected mode. The TRIG in- is aborted and OUT switches high without delay. With RE-
put to OUT transition relation is always opposite in polarity, SET high, OUT remains high. When RESET switches low
with the exception of One-Shot mode. (See Mode definitions with TRIG low in any mode, OUT remains high. When RE-
above.) TRIG input has an internal pull-down resistor of SET switches low with TRIG high in Delayed Operate and
about 500k and is buffered by a Schmitt trigger to provide Dual Delay modes, the delay timer is started and OUT
input hysteresis.
switches low at the end of the delay timeout. When RE-
SET switches low with TRIG high in Delayed Release
LS7211N TIME BASE Input (RC/CLOCK, Pin 4)
mode, OUT switches low without delay. When RESET
For LS7211N, the basic timing signal is applied at the RC/ switches low with TRIG high in One-Shot mode, OUT re-
CLOCK input. The clock can be provided from either an ex- mains high. RESET input has an internal pull-down resistor
ternal source or generated by an internal oscillator by con- of about 500k, and is buffered by a Schmitt Trigger to
necting an R-C network to this input.
provide input hysteresis.
The frequency of oscillation is given by ƒ 1/RC. Chip-to-
chip oscillation tolerance is ± 5% for a fixed value of RC.
The minimum resistance, R MIN = 4000, VDD = + 4V
VSS (-V, Pin 8)
Supply voltage negative terminal or GND.
= 1200, VDD = +10V
= 600, VDD = +18V
DELAY Output (OUT, Pin 9)
Except in One-Shot mode, OUT switches with or without
The external clock mode is selected by applying a logic low delay (depending on mode) in inverse relation to the logic
to the RCS/CLKS input (Pin 5); the internal oscillator mode is level of the TRIG input. In One-Shot mode, a timed low
selected by applying a high level to the RCS/CLKS input.
level is produced at OUT, in response to a positive transi-
tion of the TRIG input.
LS7212N TIME BASE Input (XTLI/CLOCK, Pin 4)
For LS7212N, the basic timing clock is applied to the XLTI/ WEIGHTING BIT Inputs (WB7 to WB0, Pins 10 - 17)
CLOCK input from either an external clock source or gener- Inputs WB0 through WB7 are binary weighted delay bits
ated by an internal crystal oscillator by connecting a crystal used to program the delay according to the following
between XTLI/CLOCK input and the XTLO output (Pin 5).
relations:
LS7211N TIME BASE SELECT Input (RCS/CLKS, Pin 5) One-Shot Mode: Pulse width = SW
For LS7211N, the external clock operation at Pin 4 is se-
ƒ
lected by applying a logic low to the RCS/CLKS input. The in-
ternal oscillator option with RC timer at Pin 4 is selected by All other Modes: Delay = SW + 0.5
applying a logic high at the RCS/CLKS input. RCS/CLKS in-
ƒ
put has an internal pull-down resistor of about 500k.
Where:
S = Prescale factor (See Table 2)
LS7212N TIME BASE Output (XTLO, Pin 5)
ƒ = Time base frequency at Pin 4
For LS7212N, when a crystal is used for generating the time W = WB0 + WB1 + ....... WB7
base oscillation, the crystal is connected between XTLI/
CLOCK and XTLO pins.
The weighting factor W is calculated by substituting in the
equation above for W, the weighted values for all the WB
PRESCALER SELECT Input (PSCLS, Pin 6)
inputs that are at logic high. The weighted values for the
The PSCLS input is a 3-state input, which selects one of WB inputs are shown in Table 3. Each WB input has an in-
three prescale factors according to Table 2.
ternal pull-down resistor of about 500k.
TABLE 2. PRESCALE FACTOR SELECTION
TABLE 3. BIT WEIGHTS
PSCLS Input
Logic Level
Float
VSS
VDD
S (Prescale Factor )
LS7211N
LS7212N
11
3,000
32,768
3,600
32,768x60
Using prescale factors of 3000 and 3600, delays in units of
minutes can be produced from 50Hz and 60Hz line sources.
Prescale factors of 32,768 and 32,768 x 60 can be used to
generate accurate delays in units of seconds and minutes,
respectively, from a 32kHz watch crystal.
BITS
WB0
WB1
WB2
WB3
WB4
WB5
WB6
WB7
VDD (+V, Pin 3)
Supply voltage positive terminal.
VALUE
1
2
4
8
16
32
64
128
7211N-062209-2



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ABSOLUTE MAXIMUM RATINGS: (All voltages referenced to VSS)
SYMBOL
VALUE
DC Supply Voltage
VDD +19
Voltage (Any Pin)
VIN VSS - 0.3 to VDD + 0.3
Operating Temperature
TA -20 to +85
Storage Temperature
TSTG
-65 to +150
ELECTRICAL CHARACTERISTICS (Voltages referenced to Vss)
Characteristic
SYMBOL VDD
Supply Voltage
Supply Current
Input Voltages:
Reset, Trigger Low
Reset, Trigger High
Reset, Trigger Hysteresis
All other inputs, Low
All other inputs, High
Input Currents:
PSCLS Low
PSCLS High
A, B Low
A, B High
All other inputs, Low
All other inputs, High
Output Current:
OUT Sink
OUT Source
VDD
IDD
VTL
VTH
VIL
VIH
IPL
IPH
IML
IMH
IIL
IIH
IOSNK
IOSRC
-
3.0
10.0
18.0
3.0
10.0
18.0
3.0
10.0
18.0
3.0
10.0
18.0
3.0
10.0
18.0
3.0
10.0
18.0
3.0
10.0
18.0
3.0
10.0
18.0
3.0
10.0
18.0
-
-
3.0
10.0
18.0
3.0
10.0
18.0
3.0
10.0
18.0
-20°C
Min Max
3.0 18.0
- 66
- 252
- 540
-
-
-
2.2
6.1
9.7
0.7
2.2
3.9
-
-
-
1.9
6.5
13.3
0.8
2.3
3.9
-
-
-
-
-
-
1.1
4.5
10.6
-
-
-
- 3.2
- 31
- 84
- 9.8
- 31
- 85
- 6.0
- 59
- 157
- 100
- 100
- 33
- 120
- 121
13.2
26
30.7
4.1
7.2
8.2
-
-
-
-
-
-
+25°C
Min Max
3.0 18.0
- 55
- 210
- 450
-
-
-
2.1
6.0
10.5
0.7
2.2
3.9
-
-
-
1.9
6.5
13.3
0.75
2.2
3.8
-
-
-
-
-
-
1.1
4.5
10.6
-
-
-
- 2.5
- 24
- 65
- 7.5
- 24
- 65
- 5.0
- 48
- 128
- 100
- 100
- 27
- 105
- 107
10.1
19.7
23.6
3.2
5.5
6.3
-
-
-
-
-
-
UNIT
V
V
°C
°C
+85°C
Min Max
3.0 18.0
- 44
- 168
- 360
-
-
-
2.0
5.9
11.0
0.7
2.2
3.9
-
-
-
1.9
6.5
13.3
0.7
2.1
3.7
-
-
-
-
-
-
1.1
4.5
10.6
-
-
-
- 1.9
- 18
- 49
- 5.8
- 18.2
- 49
- 4.0
- 38
- 98
- 200
- 200
- 23
- 81
- 82
7.0 -
15 -
17 -
2.1 -
4.1 -
4.6 -
Unit Condition
V-
µA
µA with the clock off and
µA all inputs floating.
V
V-
V
V
V-
V
V
V-
V
V
V-
V
V
V-
V
µA
µA Input at VSS
µA
µA
µA Input at VDD
µA
µA
µA Input at VSS
µA
nA Input at VDD
nA Input at VSS
µA
µA Input at VDD
µA
mA
mA Vo = +0.5V
mA
mA
mA Vo = VDD - 0.5V
mA
7211N-072009-3



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ELECTRICAL CHARACTERISTICS (Voltages referenced to Vss) (Con’t)
Characteristic
SYMBOL VDD
Min Max Min Max
Switching Characteristics (See Fig. 3)
3.0 - 1.8 - 1.4
RC Oscillator Frequency
fosc 10.0
-
4.5 -
3.4
18.0
-
8.0 -
4.0
3.0 - 2.6 - 2.0
External Clock or
fext 10.0
-
5.3 -
4.0
Crystal Oscillator
18.0 -
5.9 -
4.5
Frequency
3.0 - 7.2 -
5.5
fext 10.0
-
16.0
-
12.8
18.0
-
15.9
-
13.0
TRIG Set-Up Time
A, B Set-Up Time
WB0 - WB7 Set-Up Time
Clock to Out Delay
t1 - 39 - 50 -
t2 - 0 - 0 -
t3 - 0 - 0 -
3.0 - 284 - 375
t4 10.0
-
98 - 130
18.0
-
87 - 115
+V
A1
500k
+V
MODE
REG
B2
500k
EDGE
DETECT
TRIG 18
500k
LATCH
Min Max
- 1.05
- 2.6
- 3.0
- 1.52
- 3.0
- 3.5
- 4.2
- 9.7
- 9.1
66 -
0-
0-
- 495
- 172
- 152
CONTROL
LOGIC
Unit Condition
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
-
For prescale
factor S = 1 or 3,000
or 3,600
S = 32,768
or
32,768 x 60
ns -
ns -
ns -
ns
ns CL = 50pF
ns
BUF
9 OUT
RESET 7
CLOCK/RC/XTLI 4
XTLO (LS7212N) 5
500k
CLOCK
OSC
MUX
LATCH/TIMER
8
10-17 WB7-WB0
500k (8)
PRESCALER
RCS/CLKS (LS7211N) 5
500k
PSCLS 6
+V
1M
1M
3-STATE
DECODER
+V
-V (Gnd)
3 VDD
8 VSS
7211N-072009-4
FIGURE 2. LS7211N / LS7212N BLOCK DIAGRAM



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